Remove uses of unreachable_unchecked

taiki-e · taiki-e · commit d50bc0f7c6e5 · 2023-05-11T22:32:58.000+09:00
See taiki-e/portable-atomic@8148fda for the context.
diff --git a/src/arch/aarch64.rs b/src/arch/aarch64.rs
@@ -54,7 +54,7 @@ macro_rules! atomic_rmw {
             // https://reviews.llvm.org/D141748
             #[cfg(target_env = "msvc")]
             Ordering::SeqCst => $op!("a", "l", "dmb ish"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -106,7 +106,7 @@ macro_rules! atomic {
                         #[cfg(not(any(target_feature = "rcpc", atomic_maybe_uninit_target_feature = "rcpc")))]
                         Ordering::Acquire => atomic_load!("a"),
                         Ordering::SeqCst => atomic_load!("a"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -148,7 +148,7 @@ macro_rules! atomic {
                         // https://reviews.llvm.org/D141748
                         #[cfg(target_env = "msvc")]
                         Ordering::SeqCst => atomic_store!("l", "dmb ish"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -471,7 +471,7 @@ macro_rules! atomic128 {
                                 options(nostack, preserves_flags),
                             );
                         },
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
                 #[cfg(not(any(target_feature = "lse2", atomic_maybe_uninit_target_feature = "lse2")))]
@@ -524,7 +524,7 @@ macro_rules! atomic128 {
                         Ordering::Relaxed => atomic_load!("", ""),
                         Ordering::Acquire => atomic_load!("a", ""),
                         Ordering::SeqCst => atomic_load!("a", "l"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -565,7 +565,7 @@ macro_rules! atomic128 {
                         Ordering::Relaxed => atomic_store!("", ""),
                         Ordering::Release => atomic_store!("", "dmb ish"),
                         Ordering::SeqCst => atomic_store!("dmb ish", "dmb ish"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
                 #[cfg(not(any(target_feature = "lse2", atomic_maybe_uninit_target_feature = "lse2")))]
diff --git a/src/arch/arm.rs b/src/arch/arm.rs
@@ -145,7 +145,7 @@ macro_rules! atomic {
                         Ordering::Relaxed => atomic_load!(asm_no_dmb, ""),
                         // Acquire and SeqCst loads are equivalent.
                         Ordering::Acquire | Ordering::SeqCst => atomic_load!(asm_use_dmb, dmb!()),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -182,7 +182,7 @@ macro_rules! atomic {
                         Ordering::Relaxed => atomic_store!(asm_no_dmb, "", ""),
                         Ordering::Release => atomic_store!(asm_use_dmb, "", dmb!()),
                         Ordering::SeqCst => atomic_store!(asm_use_dmb, dmb!(), dmb!()),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -242,7 +242,7 @@ macro_rules! atomic {
                         Ordering::AcqRel | Ordering::SeqCst => {
                             atomic_swap!(asm_use_dmb, dmb!(), dmb!());
                         }
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -399,7 +399,7 @@ macro_rules! atomic {
                         // AcqRel and SeqCst compare_exchange are equivalent.
                         (AcqRel | SeqCst, Relaxed) => cmpxchg_acqrel!(""),
                         (AcqRel | SeqCst, _) => cmpxchg_acqrel!(dmb!()),
-                        _ => unreachable_unchecked!("{:?}, {:?}", success, failure),
+                        _ => unreachable!("{:?}, {:?}", success, failure),
                     }
                     debug_assert!(r == 0 || r == 1, "r={}", r);
                     // 0 if the store was successful, 1 if no store was performed
@@ -539,7 +539,7 @@ macro_rules! atomic {
                         // AcqRel and SeqCst compare_exchange_weak are equivalent.
                         (AcqRel | SeqCst, Relaxed) => cmpxchg_weak_fail_load_relaxed!(dmb!()),
                         (AcqRel | SeqCst, _) => cmpxchg_weak!(asm_use_dmb, dmb!(), dmb!()),
-                        _ => unreachable_unchecked!("{:?}, {:?}", success, failure),
+                        _ => unreachable!("{:?}, {:?}", success, failure),
                     }
                     debug_assert!(r == 0 || r == 1, "r={}", r);
                     // 0 if the store was successful, 1 if no store was performed
@@ -600,7 +600,7 @@ macro_rules! atomic64 {
                         Ordering::Relaxed => atomic_load!(asm_no_dmb, ""),
                         // Acquire and SeqCst loads are equivalent.
                         Ordering::Acquire | Ordering::SeqCst => atomic_load!(asm_use_dmb, dmb!()),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -652,7 +652,7 @@ macro_rules! atomic64 {
                         Ordering::Relaxed => atomic_store!(asm_no_dmb, "", ""),
                         Ordering::Release => atomic_store!(asm_use_dmb, "", dmb!()),
                         Ordering::SeqCst => atomic_store!(asm_use_dmb, dmb!(), dmb!()),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -711,7 +711,7 @@ macro_rules! atomic64 {
                         Ordering::Release => atomic_swap!(asm_use_dmb, "", dmb!()),
                         // AcqRel and SeqCst swaps are equivalent.
                         Ordering::AcqRel | Ordering::SeqCst => atomic_swap!(asm_use_dmb, dmb!(), dmb!()),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -892,7 +892,7 @@ macro_rules! atomic64 {
                         // AcqRel and SeqCst compare_exchange are equivalent.
                         (AcqRel | SeqCst, Relaxed) => cmpxchg_acqrel!(""),
                         (AcqRel | SeqCst, _) => cmpxchg_acqrel!(dmb!()),
-                        _ => unreachable_unchecked!("{:?}, {:?}", success, failure),
+                        _ => unreachable!("{:?}, {:?}", success, failure),
                     }
                     debug_assert!(r == 0 || r == 1, "r={}", r);
                     // 0 if the store was successful, 1 if no store was performed
@@ -1059,7 +1059,7 @@ macro_rules! atomic64 {
                         // AcqRel and SeqCst compare_exchange_weak are equivalent.
                         (AcqRel | SeqCst, Relaxed) => cmpxchg_weak_fail_load_relaxed!(dmb!()),
                         (AcqRel | SeqCst, _) => cmpxchg_weak!(asm_use_dmb, dmb!(), dmb!()),
-                        _ => unreachable_unchecked!("{:?}, {:?}", success, failure),
+                        _ => unreachable!("{:?}, {:?}", success, failure),
                     }
                     debug_assert!(r == 0 || r == 1, "r={}", r);
                     // 0 if the store was successful, 1 if no store was performed
diff --git a/src/arch/armv8.rs b/src/arch/armv8.rs
@@ -31,7 +31,7 @@ macro_rules! atomic_rmw {
             Ordering::Release => $op!("r", "l"),
             // AcqRel and SeqCst RMWs are equivalent.
             Ordering::AcqRel | Ordering::SeqCst => $op!("a", "l"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -68,7 +68,7 @@ macro_rules! atomic {
                         Ordering::Relaxed => atomic_load!("r"),
                         // Acquire and SeqCst loads are equivalent.
                         Ordering::Acquire | Ordering::SeqCst => atomic_load!("a"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -103,7 +103,7 @@ macro_rules! atomic {
                         Ordering::Relaxed => atomic_store!("r"),
                         // Release and SeqCst stores are equivalent.
                         Ordering::Release | Ordering::SeqCst => atomic_store!("l"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -320,7 +320,7 @@ macro_rules! atomic64 {
                         Ordering::Relaxed => atomic_load!("r"),
                         // Acquire and SeqCst loads are equivalent.
                         Ordering::Acquire | Ordering::SeqCst => atomic_load!("a"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
diff --git a/src/arch/mips.rs b/src/arch/mips.rs
@@ -48,7 +48,7 @@ macro_rules! atomic_rmw {
             Ordering::Release => $op!("", "sync"),
             // AcqRel and SeqCst RMWs are equivalent.
             Ordering::AcqRel | Ordering::SeqCst => $op!("sync", "sync"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -89,7 +89,7 @@ macro_rules! atomic_load_store {
                         Ordering::Relaxed => atomic_load!(""),
                         // Acquire and SeqCst loads are equivalent.
                         Ordering::Acquire | Ordering::SeqCst => atomic_load!("sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
diff --git a/src/arch/powerpc.rs b/src/arch/powerpc.rs
@@ -82,7 +82,7 @@ macro_rules! atomic_rmw {
             Ordering::Release => $op!("", "lwsync"),
             Ordering::AcqRel => $op!("lwsync", "lwsync"),
             Ordering::SeqCst => $op!("lwsync", "sync"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -139,7 +139,7 @@ macro_rules! atomic_load_store {
                         }
                         Ordering::Acquire => atomic_load_acquire!(""),
                         Ordering::SeqCst =>  atomic_load_acquire!("sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
                 #[cfg(target_arch = "powerpc")]
@@ -165,7 +165,7 @@ macro_rules! atomic_load_store {
                         Ordering::Relaxed => atomic_load!("", ""),
                         Ordering::Acquire => atomic_load!("lwsync", ""),
                         Ordering::SeqCst => atomic_load!("lwsync", "sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -201,7 +201,7 @@ macro_rules! atomic_load_store {
                         Ordering::Relaxed => atomic_store!(""),
                         Ordering::Release => atomic_store!("lwsync"),
                         Ordering::SeqCst => atomic_store!("sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -1096,7 +1096,7 @@ macro_rules! atomic128 {
                         }
                         Ordering::Acquire => atomic_load_acquire!(""),
                         Ordering::SeqCst =>  atomic_load_acquire!("sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -1136,7 +1136,7 @@ macro_rules! atomic128 {
                         Ordering::Relaxed => atomic_store!(""),
                         Ordering::Release => atomic_store!("lwsync"),
                         Ordering::SeqCst => atomic_store!("sync"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
diff --git a/src/arch/riscv.rs b/src/arch/riscv.rs
@@ -89,7 +89,7 @@ macro_rules! atomic_rmw_amo {
             Ordering::Release => $op!(".rl"),
             // AcqRel and SeqCst RMWs are equivalent.
             Ordering::AcqRel | Ordering::SeqCst => $op!(".aqrl"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -102,7 +102,7 @@ macro_rules! atomic_rmw_lr_sc {
             Ordering::Release => $op!("", ".rl"),
             Ordering::AcqRel => $op!(".aq", ".rl"),
             Ordering::SeqCst => $op!(".aqrl", ".rl"),
-            _ => unreachable_unchecked!("{:?}", $order),
+            _ => unreachable!("{:?}", $order),
         }
     };
 }
@@ -142,7 +142,7 @@ macro_rules! atomic_load_store {
                         Ordering::Relaxed => atomic_load!("", ""),
                         Ordering::Acquire => atomic_load!("fence r, rw", ""),
                         Ordering::SeqCst => atomic_load!("fence r, rw", "fence rw, rw"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -178,7 +178,7 @@ macro_rules! atomic_load_store {
                         Ordering::Relaxed => atomic_store!(""),
                         // Release and SeqCst stores are equivalent.
                         Ordering::Release | Ordering::SeqCst => atomic_store!("fence rw, w"),
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
diff --git a/src/arch/s390x.rs b/src/arch/s390x.rs
@@ -84,7 +84,7 @@ macro_rules! atomic_load_store {
                                 options(nostack, preserves_flags),
                             );
                         },
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -498,7 +498,7 @@ macro_rules! atomic128 {
                                 options(nostack, preserves_flags),
                             );
                         }
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
diff --git a/src/arch/x86.rs b/src/arch/x86.rs
@@ -120,7 +120,7 @@ macro_rules! atomic {
                                 options(nostack, preserves_flags),
                             );
                         }
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
             }
@@ -377,7 +377,7 @@ macro_rules! atomic64 {
                                 options(nostack),
                             );
                         }
-                        _ => unreachable_unchecked!("{:?}", order),
+                        _ => unreachable!("{:?}", order),
                     }
                 }
                 #[cfg(not(target_feature = "sse"))]
diff --git a/src/lib.rs b/src/lib.rs
@@ -325,7 +325,6 @@ impl<T: Primitive> AtomicMaybeUninit<T> {
     where
         T: AtomicSwap,
     {
-        utils::assert_swap_ordering(order);
         let mut out = MaybeUninit::<T>::uninit();
         // SAFETY: any data races are prevented by atomic intrinsics and the raw
         // pointer passed in is valid because we got it from a reference.
diff --git a/src/utils.rs b/src/utils.rs
@@ -10,33 +10,6 @@ macro_rules! static_assert {
     };
 }
 
-/// Informs the compiler that this point in the code is not reachable, enabling
-/// further optimizations.
-///
-/// In release mode, this macro calls `core::hint::unreachable_unchecked`.
-/// In debug mode, this macro calls `unreachable!` just in case.
-///
-/// Note: When using `unreachable!`, the compiler cannot eliminate the
-/// unreachable branch in some compiler versions, even if the only pattern not
-/// covered is `#[non_exhaustive]`: <https://godbolt.org/z/68MnGa4o5>
-///
-/// # Safety
-///
-/// Reaching this function is completely undefined behavior.
-#[allow(unused_macros)]
-macro_rules! unreachable_unchecked {
-    ($($tt:tt)*) => {
-        if cfg!(debug_assertions) {
-            unreachable!($($tt)*);
-        } else {
-            // SAFETY: the caller must uphold the safety contract.
-            // (To force the caller to use unsafe block for this macro, do not use
-            // unsafe block here.)
-            core::hint::unreachable_unchecked()
-        }
-    };
-}
-
 /// Make the given function const if the given condition is true.
 macro_rules! const_fn {
     (
@@ -77,21 +50,6 @@ pub(crate) fn assert_store_ordering(order: Ordering) {
     }
 }
 
-// We use unreachable_unchecked! macro to remove the panic path (see also macro docs).
-// Since Ordering is non_exhaustive, the caller of such a function must use this
-// assertion to prevent UB due to the addition of new orderings.
-#[inline]
-pub(crate) fn assert_swap_ordering(order: Ordering) {
-    match order {
-        Ordering::AcqRel
-        | Ordering::Acquire
-        | Ordering::Relaxed
-        | Ordering::Release
-        | Ordering::SeqCst => {}
-        _ => unreachable!("{:?}", order),
-    }
-}
-
 // https://github.com/rust-lang/rust/blob/1.69.0/library/core/src/sync/atomic.rs#L3226
 #[inline]
 #[cfg_attr(debug_assertions, track_caller)]

Original file line number	Diff line number	Diff line change
`@@ -54,7 +54,7 @@ macro_rules! atomic_rmw {`
`54`	`54`	`// https://reviews.llvm.org/D141748`
`55`	`55`	`#[cfg(target_env = "msvc")]`
`56`	`56`	`Ordering::SeqCst => $op!("a", "l", "dmb ish"),`
`57`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`57`	`+ _ => unreachable!("{:?}", $order),`
`58`	`58`	`}`
`59`	`59`	`};`
`60`	`60`	`}`
`@@ -106,7 +106,7 @@ macro_rules! atomic {`
`106`	`106`	`#[cfg(not(any(target_feature = "rcpc", atomic_maybe_uninit_target_feature = "rcpc")))]`
`107`	`107`	`Ordering::Acquire => atomic_load!("a"),`
`108`	`108`	`Ordering::SeqCst => atomic_load!("a"),`
`109`		`- _ => unreachable_unchecked!("{:?}", order),`
	`109`	`+ _ => unreachable!("{:?}", order),`
`110`	`110`	`}`
`111`	`111`	`}`
`112`	`112`	`}`
`@@ -148,7 +148,7 @@ macro_rules! atomic {`
`148`	`148`	`// https://reviews.llvm.org/D141748`
`149`	`149`	`#[cfg(target_env = "msvc")]`
`150`	`150`	`Ordering::SeqCst => atomic_store!("l", "dmb ish"),`
`151`		`- _ => unreachable_unchecked!("{:?}", order),`
	`151`	`+ _ => unreachable!("{:?}", order),`
`152`	`152`	`}`
`153`	`153`	`}`
`154`	`154`	`}`
`@@ -471,7 +471,7 @@ macro_rules! atomic128 {`
`471`	`471`	`options(nostack, preserves_flags),`
`472`	`472`	`);`
`473`	`473`	`},`
`474`		`- _ => unreachable_unchecked!("{:?}", order),`
	`474`	`+ _ => unreachable!("{:?}", order),`
`475`	`475`	`}`
`476`	`476`	`}`
`477`	`477`	`#[cfg(not(any(target_feature = "lse2", atomic_maybe_uninit_target_feature = "lse2")))]`
`@@ -524,7 +524,7 @@ macro_rules! atomic128 {`
`524`	`524`	`Ordering::Relaxed => atomic_load!("", ""),`
`525`	`525`	`Ordering::Acquire => atomic_load!("a", ""),`
`526`	`526`	`Ordering::SeqCst => atomic_load!("a", "l"),`
`527`		`- _ => unreachable_unchecked!("{:?}", order),`
	`527`	`+ _ => unreachable!("{:?}", order),`
`528`	`528`	`}`
`529`	`529`	`}`
`530`	`530`	`}`
`@@ -565,7 +565,7 @@ macro_rules! atomic128 {`
`565`	`565`	`Ordering::Relaxed => atomic_store!("", ""),`
`566`	`566`	`Ordering::Release => atomic_store!("", "dmb ish"),`
`567`	`567`	`Ordering::SeqCst => atomic_store!("dmb ish", "dmb ish"),`
`568`		`- _ => unreachable_unchecked!("{:?}", order),`
	`568`	`+ _ => unreachable!("{:?}", order),`
`569`	`569`	`}`
`570`	`570`	`}`
`571`	`571`	`#[cfg(not(any(target_feature = "lse2", atomic_maybe_uninit_target_feature = "lse2")))]`
Original file line number	Diff line number	Diff line change
`@@ -145,7 +145,7 @@ macro_rules! atomic {`
`145`	`145`	`Ordering::Relaxed => atomic_load!(asm_no_dmb, ""),`
`146`	`146`	`// Acquire and SeqCst loads are equivalent.`
`147`	`147`	`Ordering::Acquire \| Ordering::SeqCst => atomic_load!(asm_use_dmb, dmb!()),`
`148`		`- _ => unreachable_unchecked!("{:?}", order),`
	`148`	`+ _ => unreachable!("{:?}", order),`
`149`	`149`	`}`
`150`	`150`	`}`
`151`	`151`	`}`
`@@ -182,7 +182,7 @@ macro_rules! atomic {`
`182`	`182`	`Ordering::Relaxed => atomic_store!(asm_no_dmb, "", ""),`
`183`	`183`	`Ordering::Release => atomic_store!(asm_use_dmb, "", dmb!()),`
`184`	`184`	`Ordering::SeqCst => atomic_store!(asm_use_dmb, dmb!(), dmb!()),`
`185`		`- _ => unreachable_unchecked!("{:?}", order),`
	`185`	`+ _ => unreachable!("{:?}", order),`
`186`	`186`	`}`
`187`	`187`	`}`
`188`	`188`	`}`
`@@ -242,7 +242,7 @@ macro_rules! atomic {`
`242`	`242`	`Ordering::AcqRel \| Ordering::SeqCst => {`
`243`	`243`	`atomic_swap!(asm_use_dmb, dmb!(), dmb!());`
`244`	`244`	`}`
`245`		`- _ => unreachable_unchecked!("{:?}", order),`
	`245`	`+ _ => unreachable!("{:?}", order),`
`246`	`246`	`}`
`247`	`247`	`}`
`248`	`248`	`}`
`@@ -399,7 +399,7 @@ macro_rules! atomic {`
`399`	`399`	`// AcqRel and SeqCst compare_exchange are equivalent.`
`400`	`400`	`(AcqRel \| SeqCst, Relaxed) => cmpxchg_acqrel!(""),`
`401`	`401`	`(AcqRel \| SeqCst, _) => cmpxchg_acqrel!(dmb!()),`
`402`		`- _ => unreachable_unchecked!("{:?}, {:?}", success, failure),`
	`402`	`+ _ => unreachable!("{:?}, {:?}", success, failure),`
`403`	`403`	`}`
`404`	`404`	`debug_assert!(r == 0 \|\| r == 1, "r={}", r);`
`405`	`405`	`// 0 if the store was successful, 1 if no store was performed`
`@@ -539,7 +539,7 @@ macro_rules! atomic {`
`539`	`539`	`// AcqRel and SeqCst compare_exchange_weak are equivalent.`
`540`	`540`	`(AcqRel \| SeqCst, Relaxed) => cmpxchg_weak_fail_load_relaxed!(dmb!()),`
`541`	`541`	`(AcqRel \| SeqCst, _) => cmpxchg_weak!(asm_use_dmb, dmb!(), dmb!()),`
`542`		`- _ => unreachable_unchecked!("{:?}, {:?}", success, failure),`
	`542`	`+ _ => unreachable!("{:?}, {:?}", success, failure),`
`543`	`543`	`}`
`544`	`544`	`debug_assert!(r == 0 \|\| r == 1, "r={}", r);`
`545`	`545`	`// 0 if the store was successful, 1 if no store was performed`
`@@ -600,7 +600,7 @@ macro_rules! atomic64 {`
`600`	`600`	`Ordering::Relaxed => atomic_load!(asm_no_dmb, ""),`
`601`	`601`	`// Acquire and SeqCst loads are equivalent.`
`602`	`602`	`Ordering::Acquire \| Ordering::SeqCst => atomic_load!(asm_use_dmb, dmb!()),`
`603`		`- _ => unreachable_unchecked!("{:?}", order),`
	`603`	`+ _ => unreachable!("{:?}", order),`
`604`	`604`	`}`
`605`	`605`	`}`
`606`	`606`	`}`
`@@ -652,7 +652,7 @@ macro_rules! atomic64 {`
`652`	`652`	`Ordering::Relaxed => atomic_store!(asm_no_dmb, "", ""),`
`653`	`653`	`Ordering::Release => atomic_store!(asm_use_dmb, "", dmb!()),`
`654`	`654`	`Ordering::SeqCst => atomic_store!(asm_use_dmb, dmb!(), dmb!()),`
`655`		`- _ => unreachable_unchecked!("{:?}", order),`
	`655`	`+ _ => unreachable!("{:?}", order),`
`656`	`656`	`}`
`657`	`657`	`}`
`658`	`658`	`}`
`@@ -711,7 +711,7 @@ macro_rules! atomic64 {`
`711`	`711`	`Ordering::Release => atomic_swap!(asm_use_dmb, "", dmb!()),`
`712`	`712`	`// AcqRel and SeqCst swaps are equivalent.`
`713`	`713`	`Ordering::AcqRel \| Ordering::SeqCst => atomic_swap!(asm_use_dmb, dmb!(), dmb!()),`
`714`		`- _ => unreachable_unchecked!("{:?}", order),`
	`714`	`+ _ => unreachable!("{:?}", order),`
`715`	`715`	`}`
`716`	`716`	`}`
`717`	`717`	`}`
`@@ -892,7 +892,7 @@ macro_rules! atomic64 {`
`892`	`892`	`// AcqRel and SeqCst compare_exchange are equivalent.`
`893`	`893`	`(AcqRel \| SeqCst, Relaxed) => cmpxchg_acqrel!(""),`
`894`	`894`	`(AcqRel \| SeqCst, _) => cmpxchg_acqrel!(dmb!()),`
`895`		`- _ => unreachable_unchecked!("{:?}, {:?}", success, failure),`
	`895`	`+ _ => unreachable!("{:?}, {:?}", success, failure),`
`896`	`896`	`}`
`897`	`897`	`debug_assert!(r == 0 \|\| r == 1, "r={}", r);`
`898`	`898`	`// 0 if the store was successful, 1 if no store was performed`
`@@ -1059,7 +1059,7 @@ macro_rules! atomic64 {`
`1059`	`1059`	`// AcqRel and SeqCst compare_exchange_weak are equivalent.`
`1060`	`1060`	`(AcqRel \| SeqCst, Relaxed) => cmpxchg_weak_fail_load_relaxed!(dmb!()),`
`1061`	`1061`	`(AcqRel \| SeqCst, _) => cmpxchg_weak!(asm_use_dmb, dmb!(), dmb!()),`
`1062`		`- _ => unreachable_unchecked!("{:?}, {:?}", success, failure),`
	`1062`	`+ _ => unreachable!("{:?}, {:?}", success, failure),`
`1063`	`1063`	`}`
`1064`	`1064`	`debug_assert!(r == 0 \|\| r == 1, "r={}", r);`
`1065`	`1065`	`// 0 if the store was successful, 1 if no store was performed`
Original file line number	Diff line number	Diff line change
`@@ -31,7 +31,7 @@ macro_rules! atomic_rmw {`
`31`	`31`	`Ordering::Release => $op!("r", "l"),`
`32`	`32`	`// AcqRel and SeqCst RMWs are equivalent.`
`33`	`33`	`Ordering::AcqRel \| Ordering::SeqCst => $op!("a", "l"),`
`34`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`34`	`+ _ => unreachable!("{:?}", $order),`
`35`	`35`	`}`
`36`	`36`	`};`
`37`	`37`	`}`
`@@ -68,7 +68,7 @@ macro_rules! atomic {`
`68`	`68`	`Ordering::Relaxed => atomic_load!("r"),`
`69`	`69`	`// Acquire and SeqCst loads are equivalent.`
`70`	`70`	`Ordering::Acquire \| Ordering::SeqCst => atomic_load!("a"),`
`71`		`- _ => unreachable_unchecked!("{:?}", order),`
	`71`	`+ _ => unreachable!("{:?}", order),`
`72`	`72`	`}`
`73`	`73`	`}`
`74`	`74`	`}`
`@@ -103,7 +103,7 @@ macro_rules! atomic {`
`103`	`103`	`Ordering::Relaxed => atomic_store!("r"),`
`104`	`104`	`// Release and SeqCst stores are equivalent.`
`105`	`105`	`Ordering::Release \| Ordering::SeqCst => atomic_store!("l"),`
`106`		`- _ => unreachable_unchecked!("{:?}", order),`
	`106`	`+ _ => unreachable!("{:?}", order),`
`107`	`107`	`}`
`108`	`108`	`}`
`109`	`109`	`}`
`@@ -320,7 +320,7 @@ macro_rules! atomic64 {`
`320`	`320`	`Ordering::Relaxed => atomic_load!("r"),`
`321`	`321`	`// Acquire and SeqCst loads are equivalent.`
`322`	`322`	`Ordering::Acquire \| Ordering::SeqCst => atomic_load!("a"),`
`323`		`- _ => unreachable_unchecked!("{:?}", order),`
	`323`	`+ _ => unreachable!("{:?}", order),`
`324`	`324`	`}`
`325`	`325`	`}`
`326`	`326`	`}`
Original file line number	Diff line number	Diff line change
`@@ -48,7 +48,7 @@ macro_rules! atomic_rmw {`
`48`	`48`	`Ordering::Release => $op!("", "sync"),`
`49`	`49`	`// AcqRel and SeqCst RMWs are equivalent.`
`50`	`50`	`Ordering::AcqRel \| Ordering::SeqCst => $op!("sync", "sync"),`
`51`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`51`	`+ _ => unreachable!("{:?}", $order),`
`52`	`52`	`}`
`53`	`53`	`};`
`54`	`54`	`}`
`@@ -89,7 +89,7 @@ macro_rules! atomic_load_store {`
`89`	`89`	`Ordering::Relaxed => atomic_load!(""),`
`90`	`90`	`// Acquire and SeqCst loads are equivalent.`
`91`	`91`	`Ordering::Acquire \| Ordering::SeqCst => atomic_load!("sync"),`
`92`		`- _ => unreachable_unchecked!("{:?}", order),`
	`92`	`+ _ => unreachable!("{:?}", order),`
`93`	`93`	`}`
`94`	`94`	`}`
`95`	`95`	`}`
Original file line number	Diff line number	Diff line change
`@@ -82,7 +82,7 @@ macro_rules! atomic_rmw {`
`82`	`82`	`Ordering::Release => $op!("", "lwsync"),`
`83`	`83`	`Ordering::AcqRel => $op!("lwsync", "lwsync"),`
`84`	`84`	`Ordering::SeqCst => $op!("lwsync", "sync"),`
`85`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`85`	`+ _ => unreachable!("{:?}", $order),`
`86`	`86`	`}`
`87`	`87`	`};`
`88`	`88`	`}`
`@@ -139,7 +139,7 @@ macro_rules! atomic_load_store {`
`139`	`139`	`}`
`140`	`140`	`Ordering::Acquire => atomic_load_acquire!(""),`
`141`	`141`	`Ordering::SeqCst => atomic_load_acquire!("sync"),`
`142`		`- _ => unreachable_unchecked!("{:?}", order),`
	`142`	`+ _ => unreachable!("{:?}", order),`
`143`	`143`	`}`
`144`	`144`	`}`
`145`	`145`	`#[cfg(target_arch = "powerpc")]`
`@@ -165,7 +165,7 @@ macro_rules! atomic_load_store {`
`165`	`165`	`Ordering::Relaxed => atomic_load!("", ""),`
`166`	`166`	`Ordering::Acquire => atomic_load!("lwsync", ""),`
`167`	`167`	`Ordering::SeqCst => atomic_load!("lwsync", "sync"),`
`168`		`- _ => unreachable_unchecked!("{:?}", order),`
	`168`	`+ _ => unreachable!("{:?}", order),`
`169`	`169`	`}`
`170`	`170`	`}`
`171`	`171`	`}`
`@@ -201,7 +201,7 @@ macro_rules! atomic_load_store {`
`201`	`201`	`Ordering::Relaxed => atomic_store!(""),`
`202`	`202`	`Ordering::Release => atomic_store!("lwsync"),`
`203`	`203`	`Ordering::SeqCst => atomic_store!("sync"),`
`204`		`- _ => unreachable_unchecked!("{:?}", order),`
	`204`	`+ _ => unreachable!("{:?}", order),`
`205`	`205`	`}`
`206`	`206`	`}`
`207`	`207`	`}`
`@@ -1096,7 +1096,7 @@ macro_rules! atomic128 {`
`1096`	`1096`	`}`
`1097`	`1097`	`Ordering::Acquire => atomic_load_acquire!(""),`
`1098`	`1098`	`Ordering::SeqCst => atomic_load_acquire!("sync"),`
`1099`		`- _ => unreachable_unchecked!("{:?}", order),`
	`1099`	`+ _ => unreachable!("{:?}", order),`
`1100`	`1100`	`}`
`1101`	`1101`	`}`
`1102`	`1102`	`}`
`@@ -1136,7 +1136,7 @@ macro_rules! atomic128 {`
`1136`	`1136`	`Ordering::Relaxed => atomic_store!(""),`
`1137`	`1137`	`Ordering::Release => atomic_store!("lwsync"),`
`1138`	`1138`	`Ordering::SeqCst => atomic_store!("sync"),`
`1139`		`- _ => unreachable_unchecked!("{:?}", order),`
	`1139`	`+ _ => unreachable!("{:?}", order),`
`1140`	`1140`	`}`
`1141`	`1141`	`}`
`1142`	`1142`	`}`
Original file line number	Diff line number	Diff line change
`@@ -89,7 +89,7 @@ macro_rules! atomic_rmw_amo {`
`89`	`89`	`Ordering::Release => $op!(".rl"),`
`90`	`90`	`// AcqRel and SeqCst RMWs are equivalent.`
`91`	`91`	`Ordering::AcqRel \| Ordering::SeqCst => $op!(".aqrl"),`
`92`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`92`	`+ _ => unreachable!("{:?}", $order),`
`93`	`93`	`}`
`94`	`94`	`};`
`95`	`95`	`}`
`@@ -102,7 +102,7 @@ macro_rules! atomic_rmw_lr_sc {`
`102`	`102`	`Ordering::Release => $op!("", ".rl"),`
`103`	`103`	`Ordering::AcqRel => $op!(".aq", ".rl"),`
`104`	`104`	`Ordering::SeqCst => $op!(".aqrl", ".rl"),`
`105`		`- _ => unreachable_unchecked!("{:?}", $order),`
	`105`	`+ _ => unreachable!("{:?}", $order),`
`106`	`106`	`}`
`107`	`107`	`};`
`108`	`108`	`}`
`@@ -142,7 +142,7 @@ macro_rules! atomic_load_store {`
`142`	`142`	`Ordering::Relaxed => atomic_load!("", ""),`
`143`	`143`	`Ordering::Acquire => atomic_load!("fence r, rw", ""),`
`144`	`144`	`Ordering::SeqCst => atomic_load!("fence r, rw", "fence rw, rw"),`
`145`		`- _ => unreachable_unchecked!("{:?}", order),`
	`145`	`+ _ => unreachable!("{:?}", order),`
`146`	`146`	`}`
`147`	`147`	`}`
`148`	`148`	`}`
`@@ -178,7 +178,7 @@ macro_rules! atomic_load_store {`
`178`	`178`	`Ordering::Relaxed => atomic_store!(""),`
`179`	`179`	`// Release and SeqCst stores are equivalent.`
`180`	`180`	`Ordering::Release \| Ordering::SeqCst => atomic_store!("fence rw, w"),`
`181`		`- _ => unreachable_unchecked!("{:?}", order),`
	`181`	`+ _ => unreachable!("{:?}", order),`
`182`	`182`	`}`
`183`	`183`	`}`
`184`	`184`	`}`
Original file line number	Diff line number	Diff line change
`@@ -84,7 +84,7 @@ macro_rules! atomic_load_store {`
`84`	`84`	`options(nostack, preserves_flags),`
`85`	`85`	`);`
`86`	`86`	`},`
`87`		`- _ => unreachable_unchecked!("{:?}", order),`
	`87`	`+ _ => unreachable!("{:?}", order),`
`88`	`88`	`}`
`89`	`89`	`}`
`90`	`90`	`}`
`@@ -498,7 +498,7 @@ macro_rules! atomic128 {`
`498`	`498`	`options(nostack, preserves_flags),`
`499`	`499`	`);`
`500`	`500`	`}`
`501`		`- _ => unreachable_unchecked!("{:?}", order),`
	`501`	`+ _ => unreachable!("{:?}", order),`
`502`	`502`	`}`
`503`	`503`	`}`
`504`	`504`	`}`
Original file line number	Diff line number	Diff line change
`@@ -120,7 +120,7 @@ macro_rules! atomic {`
`120`	`120`	`options(nostack, preserves_flags),`
`121`	`121`	`);`
`122`	`122`	`}`
`123`		`- _ => unreachable_unchecked!("{:?}", order),`
	`123`	`+ _ => unreachable!("{:?}", order),`
`124`	`124`	`}`
`125`	`125`	`}`
`126`	`126`	`}`
`@@ -377,7 +377,7 @@ macro_rules! atomic64 {`
`377`	`377`	`options(nostack),`
`378`	`378`	`);`
`379`	`379`	`}`
`380`		`- _ => unreachable_unchecked!("{:?}", order),`
	`380`	`+ _ => unreachable!("{:?}", order),`
`381`	`381`	`}`
`382`	`382`	`}`
`383`	`383`	`#[cfg(not(target_feature = "sse"))]`
Original file line number	Diff line number	Diff line change
`@@ -325,7 +325,6 @@ impl<T: Primitive> AtomicMaybeUninit<T> {`
`325`	`325`	`where`
`326`	`326`	`T: AtomicSwap,`
`327`	`327`	`{`
`328`		`- utils::assert_swap_ordering(order);`
`329`	`328`	`let mut out = MaybeUninit::<T>::uninit();`
`330`	`329`	`// SAFETY: any data races are prevented by atomic intrinsics and the raw`
`331`	`330`	`// pointer passed in is valid because we got it from a reference.`