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\[1] ARM's atomic swap is not available on v6-m (thumbv6m). RISC-V's atomic swap is not available on targets without the A (or G) extension such as riscv32i, riscv32imc, etc.<br>
\[1] ARM's atomic RMW operations are not available on v6-m (thumbv6m). RISC-V's atomic RMW operations are not available on targets without the A (or G) extension such as riscv32i, riscv32imc, etc.<br>
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\[2] If target features such as `lse` and `lse2` are enabled at compile-time, more efficient instructions are used.<br>
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\[3] Requires nightly due to `#![feature(asm_experimental_arch)]`.<br>
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\[4] target-cpu `pwr8`, `pwr9`, or `pwr10`.<br>
@@ -48,9 +48,6 @@ Feel free to submit an issue if your target is not supported yet.
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-[portable-atomic]: Portable atomic types including support for 128-bit atomics, atomic float, etc.
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