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jservjserv
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Merge pull request #8 from sysprog21/cleanup
Remove unused code
2 parents 0c99456 + ef27f99 commit b04d8c8

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4 files changed

+10
-156
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4 files changed

+10
-156
lines changed

‎rtl/memory_if.vh‎

Lines changed: 7 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -3,156 +3,29 @@
33

44
// Memory Interface Definitions
55
//
6-
// This file defines abstract memory interface types that can be used
7-
// for accessing frame buffer and palette data. The abstraction allows
8-
// for future extension to support standard bus protocols like Wishbone
9-
// or AXI without modifying the core rendering logic.
10-
//
11-
// Current implementation: Direct ROM access
12-
// Future options: Wishbone, AXI-Lite, custom SRAM interface
6+
// Defines abstract memory interface macros for ROM access with 1-cycle latency.
7+
// Optimized for FPGA block RAM inference.
138

149
`ifndef MEMORY_IF_VH
1510
`define MEMORY_IF_VH
1611

17-
// ============================================================================
18-
// Memory Interface Types
19-
// ============================================================================
20-
21-
// Define memory interface type (can be extended in future)
22-
// Currently only ROM is implemented, but architecture supports:
23-
// - ROM: Direct embedded memory (current implementation)
24-
// - WISHBONE: Wishbone Classic bus protocol
25-
// - AXI: AXI4-Lite protocol
26-
// - SRAM: External SRAM interface
27-
28-
`ifndef MEM_IF_TYPE_WISHBONE
29-
`ifndef MEM_IF_TYPE_AXI
30-
`ifndef MEM_IF_TYPE_SRAM
31-
`define MEM_IF_TYPE_ROM // Default to ROM
32-
`endif
33-
`endif
34-
`endif
35-
36-
// ============================================================================
37-
// ROM Interface (Current Implementation)
38-
// ============================================================================
39-
// Direct synchronous read access with 1-cycle latency
40-
// Optimized for FPGA block RAM inference
41-
42-
`ifdef MEM_IF_TYPE_ROM
43-
// No additional signals needed - uses reg arrays with synchronous read
44-
// Read latency: 1 clock cycle
45-
// Address width: Determined by memory size
46-
// Data width: 4 bits for frame memory, 6 bits for palette
47-
`endif
48-
49-
// ============================================================================
50-
// Wishbone Interface (Future Extension)
51-
// ============================================================================
52-
// Wishbone Classic single-cycle read protocol
53-
// Reference: OpenCores Wishbone B4 specification
54-
55-
`ifdef MEM_IF_TYPE_WISHBONE
56-
// Master signals (from renderer to memory)
57-
// wire wb_cyc; // Cycle active
58-
// wire wb_stb; // Strobe (valid transaction)
59-
// wire wb_we; // Write enable (0=read, 1=write)
60-
// wire [ADDR_WIDTH-1:0] wb_adr; // Address
61-
// wire [DATA_WIDTH-1:0] wb_dat_o; // Data output (write data)
62-
63-
// Slave signals (from memory to renderer)
64-
// wire wb_ack; // Acknowledge
65-
// wire [DATA_WIDTH-1:0] wb_dat_i; // Data input (read data)
66-
67-
// Read latency: 1 clock cycle (same as ROM)
68-
// Supports pipelined access for higher throughput
69-
`endif
70-
71-
// ============================================================================
72-
// AXI4-Lite Interface (Future Extension)
73-
// ============================================================================
74-
// AXI4-Lite read-only protocol for memory-mapped access
75-
// Reference: ARM AMBA AXI4 specification
76-
77-
`ifdef MEM_IF_TYPE_AXI
78-
// Read address channel
79-
// wire axi_arvalid; // Address valid
80-
// wire [ADDR_WIDTH-1:0] axi_araddr; // Read address
81-
// wire axi_arready; // Address ready (from slave)
82-
83-
// Read data channel
84-
// wire axi_rvalid; // Read data valid (from slave)
85-
// wire [DATA_WIDTH-1:0] axi_rdata; // Read data
86-
// wire [1:0] axi_rresp; // Response status
87-
// wire axi_rready; // Read data ready
88-
89-
// Read latency: 1-2 clock cycles
90-
// More complex but industry-standard protocol
91-
`endif
92-
93-
// ============================================================================
94-
// Helper Macros for Memory Access
95-
// ============================================================================
96-
97-
// Memory read operation (abstracts underlying protocol)
12+
// Memory read operation: synchronous read with 1-cycle latency
9813
// Usage: `MEM_READ(data, memory, address)
99-
`ifdef MEM_IF_TYPE_ROM
100-
`define MEM_READ(data, memory, address) \
101-
data <= memory[address]
102-
`elsif MEM_IF_TYPE_WISHBONE
103-
// Future: Implement Wishbone read transaction
104-
`define MEM_READ(data, memory, address) \
105-
/* TODO: Wishbone read transaction */ \
14+
`define MEM_READ(data, memory, address) \
10615
data <= memory[address]
107-
`elsif MEM_IF_TYPE_AXI
108-
// Future: Implement AXI read transaction
109-
`define MEM_READ(data, memory, address) \
110-
/* TODO: AXI read transaction */ \
111-
data <= memory[address]
112-
`else
113-
`define MEM_READ(data, memory, address) \
114-
data <= memory[address]
115-
`endif
11616

117-
// Memory initialization (abstracts loading mechanism)
17+
// Memory initialization from hex file
11818
// Usage: `MEM_INIT(memory, filename)
119-
`ifdef MEM_IF_TYPE_ROM
120-
`define MEM_INIT(memory, filename) \
19+
`define MEM_INIT(memory, filename) \
12120
initial begin \
12221
$readmemh(filename, memory); \
12322
end
124-
`elsif MEM_IF_TYPE_WISHBONE
125-
// Future: External initialization through bus
126-
`define MEM_INIT(memory, filename) \
127-
/* Initialized externally via Wishbone */
128-
`elsif MEM_IF_TYPE_AXI
129-
// Future: External initialization through bus
130-
`define MEM_INIT(memory, filename) \
131-
/* Initialized externally via AXI */
132-
`else
133-
`define MEM_INIT(memory, filename) \
134-
initial begin \
135-
$readmemh(filename, memory); \
136-
end
137-
`endif
138-
139-
// ============================================================================
140-
// Memory Sizing Parameters
141-
// ============================================================================
142-
143-
// These can be overridden for different memory configurations
144-
`ifndef FRAME_MEM_ADDR_WIDTH
145-
`define FRAME_MEM_ADDR_WIDTH 16 // 64K addresses (49,152 used)
146-
`endif
14723

24+
// Memory sizing parameters (can be overridden if needed)
14825
`ifndef FRAME_MEM_DATA_WIDTH
14926
`define FRAME_MEM_DATA_WIDTH 4 // 4-bit character indices
15027
`endif
15128

152-
`ifndef PALETTE_MEM_ADDR_WIDTH
153-
`define PALETTE_MEM_ADDR_WIDTH 4 // 16 palette entries
154-
`endif
155-
15629
`ifndef PALETTE_MEM_DATA_WIDTH
15730
`define PALETTE_MEM_DATA_WIDTH 6 // 6-bit RGB (2R2G2B)
15831
`endif

‎rtl/nyancat.v‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,8 @@
1111

1212
// Nyancat Animation Display Module
1313
//
14-
// Hardware-accelerated Nyancat (Pop-Tart Cat) animation renderer with real-time
15-
// scaling and frame sequencing. Reads pre-compressed animation data from ROM
16-
// and outputs VGA-compatible color signals synchronized to pixel clock.
14+
// Reads pre-compressed animation data from ROM and outputs VGA-compatible color
15+
// signals synchronized to pixel clock.
1716
//
1817
// Architecture:
1918
// - 12-frame animation stored as 64×64 4-bit character indices
@@ -47,8 +46,6 @@ module nyancat (
4746
// Auto-scale factor based on vertical resolution (maximize display size)
4847
// Target: use full vertical height while maintaining integer scaling
4948
localparam SCALE = V_ACTIVE / FRAME_H; // Integer division for pixel-perfect scaling
50-
localparam SCALE_SHIFT = $clog2(SCALE); // Log2 of scale for bit shifting
51-
5249
localparam SCALED_W = FRAME_W * SCALE, SCALED_H = FRAME_H * SCALE;
5350
// Use H_ACTIVE and V_ACTIVE from videomode.vh instead of hardcoded values
5451
localparam OFFSET_X = (H_ACTIVE - SCALED_W) / 2, OFFSET_Y = 0; // Centering offsets

‎rtl/vga-sync-gen.v‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ module vga_sync_gen (
180180
wire [X_COORD_WIDTH-1:0] expected_x_px = hc_prev - H_BLANK;
181181
wire [Y_COORD_WIDTH-1:0] expected_y_px = vc_prev - V_BLANK;
182182
/* verilator lint_on WIDTHTRUNC */
183-
/* verilator lint_off WIDTHTRUNC */
183+
184184
always @(posedge px_clk)
185185
if (past_valid && !reset && !$past(reset)) begin
186186
if (x_px !== expected_x_px)
@@ -198,7 +198,6 @@ module vga_sync_gen (
198198
vc_prev
199199
);
200200
end
201-
/* verilator lint_on WIDTHTRUNC */
202201
`endif
203202

204203
endmodule

‎rtl/videomode.vh‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -58,9 +58,6 @@
5858
localparam V_FP = 9;
5959
localparam V_SYNC = 3;
6060
localparam V_BP = 28;
61-
62-
localparam PIXEL_CLK_MHZ = 31.5; // MHz (for documentation/simulation)
63-
localparam MODE_NAME = "VGA 640x480 @ 72Hz";
6461
`endif
6562

6663
// ============================================================================
@@ -81,9 +78,6 @@
8178
localparam V_FP = 10;
8279
localparam V_SYNC = 2;
8380
localparam V_BP = 33;
84-
85-
localparam PIXEL_CLK_MHZ = 25.175;
86-
localparam MODE_NAME = "VGA 640x480 @ 60Hz";
8781
`endif
8882

8983
// ============================================================================
@@ -104,9 +98,6 @@
10498
localparam V_FP = 1;
10599
localparam V_SYNC = 4;
106100
localparam V_BP = 23;
107-
108-
localparam PIXEL_CLK_MHZ = 40.0;
109-
localparam MODE_NAME = "SVGA 800x600 @ 60Hz";
110101
`endif
111102

112103
// ============================================================================
@@ -127,9 +118,6 @@
127118
localparam V_FP = 37;
128119
localparam V_SYNC = 6;
129120
localparam V_BP = 23;
130-
131-
localparam PIXEL_CLK_MHZ = 50.0;
132-
localparam MODE_NAME = "SVGA 800x600 @ 72Hz";
133121
`endif
134122

135123
// ============================================================================
@@ -150,9 +138,6 @@
150138
localparam V_FP = 3;
151139
localparam V_SYNC = 6;
152140
localparam V_BP = 29;
153-
154-
localparam PIXEL_CLK_MHZ = 65.0;
155-
localparam MODE_NAME = "XGA 1024x768 @ 60Hz";
156141
`endif
157142

158143
// ============================================================================

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