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Merge pull request #443 from ChinYikMing/sret-can-branch
Specify can_branch and decode the sret instruction
2 parents 69fae57 + 6f8864b commit a968310

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2 files changed

+5
-3
lines changed

2 files changed

+5
-3
lines changed

src/decode.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -826,10 +826,12 @@ static inline bool op_system(rv_insn_t *ir, const uint32_t insn)
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break;
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case 0x105: /* WFI: Wait for Interrupt */
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case 0x002: /* URET: return from traps in U-mode */
829-
case 0x102: /* SRET: return from traps in S-mode */
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case 0x202: /* HRET: return from traps in H-mode */
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/* illegal instruciton */
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/* illegal instruction */
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return false;
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case 0x102: /* SRET: return from traps in S-mode */
833+
ir->opcode = rv_insn_sret;
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break;
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case 0x302: /* MRET */
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ir->opcode = rv_insn_mret;
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break;

src/decode.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ enum op_field {
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/* RISC-V Privileged Instruction */ \
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_(wfi, 0, 4, 0, ENC(rs1, rd)) \
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_(uret, 0, 4, 0, ENC(rs1, rd)) \
80-
_(sret, 0, 4, 0, ENC(rs1, rd)) \
80+
_(sret, 1, 4, 0, ENC(rs1, rd)) \
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_(hret, 0, 4, 0, ENC(rs1, rd)) \
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_(mret, 1, 4, 0, ENC(rs1, rd)) \
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/* RV32 Zifencei Standard Extension */ \

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