Add misalignment test suite

ChinYikMing · ChinYikMing · commit a2c759e11915 · 2024-06-26T02:13:28.000+08:00
Force a variable and a function placed at a misaligned address to
trigger the all three misaligned traps. The test suite only tested the
misalignment of instruction fetch and lw/sw instruction. The
corresponding trap handler is called successfully to handle the trap.
diff --git a/src/emulate.c b/src/emulate.c
@@ -218,6 +218,10 @@ static uint32_t *csr_get_ptr(riscv_t *rv, uint32_t csr)
         return (uint32_t *) (&rv->csr_misa);
 
     /* Machine Trap Handling */
+    case CSR_MEDELEG: /* Machine Exception Delegation Register */
+        return (uint32_t *) (&rv->csr_medeleg);
+    case CSR_MIDELEG: /* Machine Interrupt Delegation Register */
+        return (uint32_t *) (&rv->csr_mideleg);
     case CSR_MSCRATCH: /* Machine Scratch Register */
         return (uint32_t *) (&rv->csr_mscratch);
     case CSR_MEPC: /* Machine Exception Program Counter */
diff --git a/src/riscv_private.h b/src/riscv_private.h
@@ -25,9 +25,9 @@
 /* CSRs */
 enum {
     /* floating point */
-    CSR_FFLAGS = 0x001,     /* Floating-point accrued exceptions */
-    CSR_FRM = 0x002,        /* Floating-point dynamic rounding mode */
-    CSR_FCSR = 0x003,       /* Floating-point control and status register */
+    CSR_FFLAGS = 0x001, /* Floating-point accrued exceptions */
+    CSR_FRM = 0x002,    /* Floating-point dynamic rounding mode */
+    CSR_FCSR = 0x003,   /* Floating-point control and status register */
 
     /* Supervisor trap setup */
     CSR_SSTATUS = 0x100,    /* Supervisor status register */
@@ -36,20 +36,20 @@ enum {
     CSR_SCOUNTEREN = 0x106, /* Supervisor counter enable */
 
     /* Supervisor trap handling */
-    CSR_SSCRATCH = 0x140,   /* Supervisor register for machine trap handlers */
-    CSR_SEPC = 0x141,       /* Supervisor exception program counter */
-    CSR_SCAUSE = 0x142,     /* Supervisor trap cause */
-    CSR_STVAL = 0x143,      /* Supervisor bad address or instruction */
-    CSR_SIP = 0x144,        /* Supervisor interrupt pending */
+    CSR_SSCRATCH = 0x140, /* Supervisor register for machine trap handlers */
+    CSR_SEPC = 0x141,     /* Supervisor exception program counter */
+    CSR_SCAUSE = 0x142,   /* Supervisor trap cause */
+    CSR_STVAL = 0x143,    /* Supervisor bad address or instruction */
+    CSR_SIP = 0x144,      /* Supervisor interrupt pending */
 
     /* Supervisor protection and translation */
-    CSR_SATP = 0x180,       /* Supervisor address translation and protection */
+    CSR_SATP = 0x180, /* Supervisor address translation and protection */
 
     /* Machine information registers */
-    CSR_MVENDORID = 0xF11,  /* Vendor ID */
-    CSR_MARCHID = 0xF12,    /* Architecture ID */
-    CSR_MIMPID = 0xF13,     /* Implementation ID */
-    CSR_MHARTID = 0xF14,    /* Hardware thread ID */
+    CSR_MVENDORID = 0xF11, /* Vendor ID */
+    CSR_MARCHID = 0xF12,   /* Architecture ID */
+    CSR_MIMPID = 0xF13,    /* Implementation ID */
+    CSR_MHARTID = 0xF14,   /* Hardware thread ID */
 
     /* Machine trap setup */
     CSR_MSTATUS = 0x300,    /* Machine status register */
@@ -61,15 +61,15 @@ enum {
     CSR_MCOUNTEREN = 0x306, /* Machine counter enable */
 
     /* machine trap handling */
-    CSR_MSCRATCH = 0x340,   /* Scratch register for machine trap handlers */
-    CSR_MEPC = 0x341,       /* Machine exception program counter */
-    CSR_MCAUSE = 0x342,     /* Machine trap cause */
-    CSR_MTVAL = 0x343,      /* Machine bad address or instruction */
-    CSR_MIP = 0x344,        /* Machine interrupt pending */
+    CSR_MSCRATCH = 0x340, /* Scratch register for machine trap handlers */
+    CSR_MEPC = 0x341,     /* Machine exception program counter */
+    CSR_MCAUSE = 0x342,   /* Machine trap cause */
+    CSR_MTVAL = 0x343,    /* Machine bad address or instruction */
+    CSR_MIP = 0x344,      /* Machine interrupt pending */
 
     /* low words */
-    CSR_CYCLE = 0xC00,      /* Cycle counter for RDCYCLE instruction */
-    CSR_TIME = 0xC01,       /* Timer for RDTIME instruction */
+    CSR_CYCLE = 0xC00, /* Cycle counter for RDCYCLE instruction */
+    CSR_TIME = 0xC01,  /* Timer for RDTIME instruction */
     CSR_INSTRET = 0xC02,
 
     /* high words */
@@ -142,22 +142,22 @@ struct riscv_internal {
 #endif
 
     /* csr registers */
-    uint64_t csr_cycle;      /* Machine cycle counter */
-    uint32_t csr_time[2];    /* Performance counter */
-    uint32_t csr_mstatus;    /* Machine status register */
-    uint32_t csr_mtvec;      /* Machine trap-handler base address */
-    uint32_t csr_misa;       /* ISA and extensions */
-    uint32_t csr_mtval;      /* Machine bad address or instruction */
-    uint32_t csr_mcause;     /* Machine trap cause */
-    uint32_t csr_mscratch;   /* Scratch register for machine trap handler */
-    uint32_t csr_mepc;       /* Machine exception program counter */
-    uint32_t csr_mip;        /* Machine interrupt pending */
-    uint32_t csr_mie;        /* Machine interrupt enable */
-    uint32_t csr_mideleg;    /* Machine interrupt delegation register */
-    uint32_t csr_medeleg;    /* Machine exception delegation register */
-    uint32_t csr_mvendorid;  /* vendor ID */
-    uint32_t csr_marchid;    /* Architecture ID */
-    uint32_t csr_mimpid;     /* Implementation ID */
+    uint64_t csr_cycle;     /* Machine cycle counter */
+    uint32_t csr_time[2];   /* Performance counter */
+    uint32_t csr_mstatus;   /* Machine status register */
+    uint32_t csr_mtvec;     /* Machine trap-handler base address */
+    uint32_t csr_misa;      /* ISA and extensions */
+    uint32_t csr_mtval;     /* Machine bad address or instruction */
+    uint32_t csr_mcause;    /* Machine trap cause */
+    uint32_t csr_mscratch;  /* Scratch register for machine trap handler */
+    uint32_t csr_mepc;      /* Machine exception program counter */
+    uint32_t csr_mip;       /* Machine interrupt pending */
+    uint32_t csr_mie;       /* Machine interrupt enable */
+    uint32_t csr_mideleg;   /* Machine interrupt delegation register */
+    uint32_t csr_medeleg;   /* Machine exception delegation register */
+    uint32_t csr_mvendorid; /* vendor ID */
+    uint32_t csr_marchid;   /* Architecture ID */
+    uint32_t csr_mimpid;    /* Implementation ID */
     uint32_t csr_mbadaddr;
 
     uint32_t csr_sstatus;    /* supervisor status register */
@@ -171,7 +171,7 @@ struct riscv_internal {
     uint32_t csr_stval;      /* supervisor trap value register */
     uint32_t csr_satp;       /* supervisor address translation and protection */
 
-    uint32_t priv_mode;      /* U-mode or S-mode or M-mode */
+    uint32_t priv_mode; /* U-mode or S-mode or M-mode */
 
     bool compressed; /**< current instruction is compressed or not */
 #if !RV32_HAS(JIT)
diff --git a/tests/system/alignment/Makefile b/tests/system/alignment/Makefile
@@ -0,0 +1,26 @@
+PREFIX ?= riscv32-unknown-elf-
+ARCH = -march=rv32izicsr
+LINKER_SCRIPT = linker.ld
+
+DEBUG_CFLAGS = -g
+CFLAGS = -c
+LDFLAGS = -T
+EXEC = misalign.elf
+
+CC = $(PREFIX)gcc
+AS = $(PREFIX)as
+LD = $(PREFIX)ld
+OBJDUMP = $(PREFIX)objdump
+
+deps = main.o misalign.o
+
+all:
+	$(CC) $(DEBUG_CLAGS) $(CFLAGS) main.c
+	$(AS) $(DEBUG_CLAGS) $(ARCH) misalign.S -o misalign.o
+	$(LD) $(LDFLAGS) $(LINKER_SCRIPT) -o $(EXEC) $(deps)
+
+dump:
+	$(OBJDUMP) -Ds $(EXEC) | less
+
+clean:
+	rm $(EXEC) $(deps)
diff --git a/tests/system/alignment/linker.ld b/tests/system/alignment/linker.ld
@@ -0,0 +1,15 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x10000;
+  .text : { *(.text) }
+  . = 0x8000003;
+  .misdata : { *(.misdata) }
+  . = 0x10000007;
+  .mistext : { *(.mistext) }
+  .data : { *(.data) }
+  .bss : { *(.bss) }
+}
diff --git a/tests/system/alignment/main.c b/tests/system/alignment/main.c
@@ -0,0 +1,61 @@
+#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); })
+
+#define CAUSE_MISALIGNED_INSN_FETCH (1U << 0x0)
+#define CAUSE_MISALIGNED_LOAD (1U << 0x4)
+#define CAUSE_MISALIGNED_STORE (1U << 0x6)
+
+#define printstr(ptr, length)                   \
+    do {                                        \
+        asm volatile(                           \
+            "add a7, x0, 0x40;"                 \
+            "add a0, x0, 0x1;" /* stdout */     \
+            "add a1, x0, %0;"                   \
+            "mv a2, %1;" /* length character */ \
+            "ecall;"                            \
+            :                                   \
+            : "r"(ptr), "r"(length)             \
+            : "a0", "a1", "a2", "a7");          \
+    } while (0)
+
+#define TEST_OUTPUT(msg, length) printstr(msg, length)
+
+#define TEST_LOGGER(msg)                 \
+    {                                    \
+        char _msg[] = msg;               \
+        TEST_OUTPUT(_msg, sizeof(_msg)); \
+    }
+
+extern int *misalign_data;
+
+extern void misalign_func();
+
+extern void misalign_trap_handler();
+
+int main()
+{
+    /* init s-mode trap handler */
+    write_csr(stvec, misalign_trap_handler);
+    write_csr(medeleg, CAUSE_MISALIGNED_INSN_FETCH | CAUSE_MISALIGNED_LOAD |
+                           CAUSE_MISALIGNED_STORE);
+
+    /* misalign load */
+    const int x = *misalign_data;
+    /* execute the registered trap handler is considered a pass (use gdb to
+     * track) */
+    TEST_LOGGER("MISALIGNED LOAD TEST PASSED!\n");
+
+    /* misalign store */
+    char *ptr = (char *) misalign_data;
+    *(int *) (ptr + 3) = x + 3;
+    /* execute the registered trap handler is considered a pass (use gdb to
+     * track) */
+    TEST_LOGGER("MISALIGNED STORE TEST PASSED!\n");
+
+    /* misalign instuction fetch */
+    misalign_func();
+    /* execute the registered trap handler is considered a pass (use gdb to
+     * track) */
+    TEST_LOGGER("MISALIGNED INSTRUCTION FETCH TEST PASSED!\n");
+
+    return 0;
+}
diff --git a/tests/system/alignment/misalign.S b/tests/system/alignment/misalign.S
@@ -0,0 +1,70 @@
+CAUSE_MISALIGNED_INSN_FETCH = 0x0
+CAUSE_MISALIGNED_LOAD  = 0x4
+CAUSE_MISALIGNED_STORE = 0x6
+
+.section .misdata, "aw", @progbits
+.global misalign_data
+.type misalign_data, @object
+misalign_data:
+    .word = 0xBAAAAAAD
+    . = 0x8000003  # force misaligned address
+
+.section .mistext, "ax", @progbits
+.global misalign_func
+.type misalign_func, @function
+misalign_func:
+    . = 0x10000007 # force misaligned address
+    addi t0, t0, 1
+
+.section .text
+.global _start
+_start:
+    call main	
+    j exit
+
+# Assume three traps are delegated to supervisor,
+# so handle them using supervisor CSR
+.global misalign_trap_handler
+misalign_trap_handler:
+    csrr t0, scause
+    
+    # Check for misaligned instruction fetch
+    li t1, CAUSE_MISALIGNED_INSN_FETCH
+    beq t0, t1, misaligned_insn_fetch_handler
+    
+    # Check for misaligned load
+    li t1, CAUSE_MISALIGNED_LOAD
+    beq t0, t1, misaligned_load_handler
+    
+    # Check for misaligned store
+    li t1, CAUSE_MISALIGNED_STORE
+    beq t0, t1, misaligned_store_handler
+    
+    # If none of the above, exit failed
+fail:
+    li a0, 1
+    j exit
+
+exit:
+    li a7, 93
+    ecall
+
+misaligned_insn_fetch_handler:
+    # simply jump back to caller since no really handling it
+    # since the rest of instruction are also misaligned
+    jalr zero, ra, 0
+
+misaligned_load_handler:
+    # Handle load misalignment: skip load
+    csrr t0, sepc
+    addi t0, t0, 4
+    csrw sepc, t0
+    sret
+
+misaligned_store_handler:
+    # Handle store misalignment: skip store
+    csrr t0, sepc
+    addi t0, t0, 4
+    csrw sepc, t0
+    sret
+
