|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | +; RUN: llc < %s | FileCheck %s |
| 3 | + |
| 4 | +target triple = "aarch64-unknown-linux-gnu" |
| 5 | + |
| 6 | +; |
| 7 | +; SABD |
| 8 | +; |
| 9 | + |
| 10 | +define <8 x i8> @sabd_8b(<8 x i8> %a, <8 x i8> %b) #0 { |
| 11 | +; CHECK-LABEL: sabd_8b: |
| 12 | +; CHECK: // %bb.0: |
| 13 | +; CHECK-NEXT: sabd v0.8b, v0.8b, v1.8b |
| 14 | +; CHECK-NEXT: ret |
| 15 | + %a.sext = sext <8 x i8> %a to <8 x i16> |
| 16 | + %b.sext = sext <8 x i8> %b to <8 x i16> |
| 17 | + %sub = sub <8 x i16> %a.sext, %b.sext |
| 18 | + %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) |
| 19 | + %trunc = trunc <8 x i16> %abs to <8 x i8> |
| 20 | + ret <8 x i8> %trunc |
| 21 | +} |
| 22 | + |
| 23 | +define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) #0 { |
| 24 | +; CHECK-LABEL: sabd_16b: |
| 25 | +; CHECK: // %bb.0: |
| 26 | +; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b |
| 27 | +; CHECK-NEXT: ret |
| 28 | + %a.sext = sext <16 x i8> %a to <16 x i16> |
| 29 | + %b.sext = sext <16 x i8> %b to <16 x i16> |
| 30 | + %sub = sub <16 x i16> %a.sext, %b.sext |
| 31 | + %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true) |
| 32 | + %trunc = trunc <16 x i16> %abs to <16 x i8> |
| 33 | + ret <16 x i8> %trunc |
| 34 | +} |
| 35 | + |
| 36 | +define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) #0 { |
| 37 | +; CHECK-LABEL: sabd_4h: |
| 38 | +; CHECK: // %bb.0: |
| 39 | +; CHECK-NEXT: sabd v0.4h, v0.4h, v1.4h |
| 40 | +; CHECK-NEXT: ret |
| 41 | + %a.sext = sext <4 x i16> %a to <4 x i32> |
| 42 | + %b.sext = sext <4 x i16> %b to <4 x i32> |
| 43 | + %sub = sub <4 x i32> %a.sext, %b.sext |
| 44 | + %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) |
| 45 | + %trunc = trunc <4 x i32> %abs to <4 x i16> |
| 46 | + ret <4 x i16> %trunc |
| 47 | +} |
| 48 | + |
| 49 | +define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) #0 { |
| 50 | +; CHECK-LABEL: sabd_4h_promoted_ops: |
| 51 | +; CHECK: // %bb.0: |
| 52 | +; CHECK-NEXT: shl v0.4h, v0.4h, #8 |
| 53 | +; CHECK-NEXT: shl v1.4h, v1.4h, #8 |
| 54 | +; CHECK-NEXT: sshr v0.4h, v0.4h, #8 |
| 55 | +; CHECK-NEXT: sshr v1.4h, v1.4h, #8 |
| 56 | +; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h |
| 57 | +; CHECK-NEXT: abs v0.4h, v0.4h |
| 58 | +; CHECK-NEXT: ret |
| 59 | + %a.sext = sext <4 x i8> %a to <4 x i16> |
| 60 | + %b.sext = sext <4 x i8> %b to <4 x i16> |
| 61 | + %sub = sub <4 x i16> %a.sext, %b.sext |
| 62 | + %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true) |
| 63 | + ret <4 x i16> %abs |
| 64 | +} |
| 65 | + |
| 66 | +define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) #0 { |
| 67 | +; CHECK-LABEL: sabd_8h: |
| 68 | +; CHECK: // %bb.0: |
| 69 | +; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h |
| 70 | +; CHECK-NEXT: ret |
| 71 | + %a.sext = sext <8 x i16> %a to <8 x i32> |
| 72 | + %b.sext = sext <8 x i16> %b to <8 x i32> |
| 73 | + %sub = sub <8 x i32> %a.sext, %b.sext |
| 74 | + %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true) |
| 75 | + %trunc = trunc <8 x i32> %abs to <8 x i16> |
| 76 | + ret <8 x i16> %trunc |
| 77 | +} |
| 78 | + |
| 79 | +define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) #0 { |
| 80 | +; CHECK-LABEL: sabd_8h_promoted_ops: |
| 81 | +; CHECK: // %bb.0: |
| 82 | +; CHECK-NEXT: sabdl v0.8h, v0.8b, v1.8b |
| 83 | +; CHECK-NEXT: ret |
| 84 | + %a.sext = sext <8 x i8> %a to <8 x i16> |
| 85 | + %b.sext = sext <8 x i8> %b to <8 x i16> |
| 86 | + %sub = sub <8 x i16> %a.sext, %b.sext |
| 87 | + %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) |
| 88 | + ret <8 x i16> %abs |
| 89 | +} |
| 90 | + |
| 91 | +define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) #0 { |
| 92 | +; CHECK-LABEL: sabd_2s: |
| 93 | +; CHECK: // %bb.0: |
| 94 | +; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s |
| 95 | +; CHECK-NEXT: ret |
| 96 | + %a.sext = sext <2 x i32> %a to <2 x i64> |
| 97 | + %b.sext = sext <2 x i32> %b to <2 x i64> |
| 98 | + %sub = sub <2 x i64> %a.sext, %b.sext |
| 99 | + %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) |
| 100 | + %trunc = trunc <2 x i64> %abs to <2 x i32> |
| 101 | + ret <2 x i32> %trunc |
| 102 | +} |
| 103 | + |
| 104 | +define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) #0 { |
| 105 | +; CHECK-LABEL: sabd_2s_promoted_ops: |
| 106 | +; CHECK: // %bb.0: |
| 107 | +; CHECK-NEXT: shl v0.2s, v0.2s, #16 |
| 108 | +; CHECK-NEXT: shl v1.2s, v1.2s, #16 |
| 109 | +; CHECK-NEXT: sshr v0.2s, v0.2s, #16 |
| 110 | +; CHECK-NEXT: sshr v1.2s, v1.2s, #16 |
| 111 | +; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s |
| 112 | +; CHECK-NEXT: abs v0.2s, v0.2s |
| 113 | +; CHECK-NEXT: ret |
| 114 | + %a.sext = sext <2 x i16> %a to <2 x i32> |
| 115 | + %b.sext = sext <2 x i16> %b to <2 x i32> |
| 116 | + %sub = sub <2 x i32> %a.sext, %b.sext |
| 117 | + %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true) |
| 118 | + ret <2 x i32> %abs |
| 119 | +} |
| 120 | + |
| 121 | +define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) #0 { |
| 122 | +; CHECK-LABEL: sabd_4s: |
| 123 | +; CHECK: // %bb.0: |
| 124 | +; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s |
| 125 | +; CHECK-NEXT: ret |
| 126 | + %a.sext = sext <4 x i32> %a to <4 x i64> |
| 127 | + %b.sext = sext <4 x i32> %b to <4 x i64> |
| 128 | + %sub = sub <4 x i64> %a.sext, %b.sext |
| 129 | + %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true) |
| 130 | + %trunc = trunc <4 x i64> %abs to <4 x i32> |
| 131 | + ret <4 x i32> %trunc |
| 132 | +} |
| 133 | + |
| 134 | +define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) #0 { |
| 135 | +; CHECK-LABEL: sabd_4s_promoted_ops: |
| 136 | +; CHECK: // %bb.0: |
| 137 | +; CHECK-NEXT: sabdl v0.4s, v0.4h, v1.4h |
| 138 | +; CHECK-NEXT: ret |
| 139 | + %a.sext = sext <4 x i16> %a to <4 x i32> |
| 140 | + %b.sext = sext <4 x i16> %b to <4 x i32> |
| 141 | + %sub = sub <4 x i32> %a.sext, %b.sext |
| 142 | + %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) |
| 143 | + ret <4 x i32> %abs |
| 144 | +} |
| 145 | + |
| 146 | +define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) #0 { |
| 147 | +; CHECK-LABEL: sabd_2d: |
| 148 | +; CHECK: // %bb.0: |
| 149 | +; CHECK-NEXT: mov x8, v0.d[1] |
| 150 | +; CHECK-NEXT: fmov x10, d0 |
| 151 | +; CHECK-NEXT: mov x9, v1.d[1] |
| 152 | +; CHECK-NEXT: asr x11, x10, #63 |
| 153 | +; CHECK-NEXT: asr x12, x8, #63 |
| 154 | +; CHECK-NEXT: asr x13, x9, #63 |
| 155 | +; CHECK-NEXT: subs x8, x8, x9 |
| 156 | +; CHECK-NEXT: fmov x9, d1 |
| 157 | +; CHECK-NEXT: sbcs x12, x12, x13 |
| 158 | +; CHECK-NEXT: asr x13, x9, #63 |
| 159 | +; CHECK-NEXT: subs x9, x10, x9 |
| 160 | +; CHECK-NEXT: sbcs x10, x11, x13 |
| 161 | +; CHECK-NEXT: cmp x10, #0 |
| 162 | +; CHECK-NEXT: cneg x9, x9, lt |
| 163 | +; CHECK-NEXT: cmp x12, #0 |
| 164 | +; CHECK-NEXT: cneg x8, x8, lt |
| 165 | +; CHECK-NEXT: fmov d0, x9 |
| 166 | +; CHECK-NEXT: fmov d1, x8 |
| 167 | +; CHECK-NEXT: mov v0.d[1], v1.d[0] |
| 168 | +; CHECK-NEXT: ret |
| 169 | + %a.sext = sext <2 x i64> %a to <2 x i128> |
| 170 | + %b.sext = sext <2 x i64> %b to <2 x i128> |
| 171 | + %sub = sub <2 x i128> %a.sext, %b.sext |
| 172 | + %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true) |
| 173 | + %trunc = trunc <2 x i128> %abs to <2 x i64> |
| 174 | + ret <2 x i64> %trunc |
| 175 | +} |
| 176 | + |
| 177 | +define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) #0 { |
| 178 | +; CHECK-LABEL: sabd_2d_promoted_ops: |
| 179 | +; CHECK: // %bb.0: |
| 180 | +; CHECK-NEXT: sabdl v0.2d, v0.2s, v1.2s |
| 181 | +; CHECK-NEXT: ret |
| 182 | + %a.sext = sext <2 x i32> %a to <2 x i64> |
| 183 | + %b.sext = sext <2 x i32> %b to <2 x i64> |
| 184 | + %sub = sub <2 x i64> %a.sext, %b.sext |
| 185 | + %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) |
| 186 | + ret <2 x i64> %abs |
| 187 | +} |
| 188 | + |
| 189 | +; |
| 190 | +; UABD |
| 191 | +; |
| 192 | + |
| 193 | +define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) #0 { |
| 194 | +; CHECK-LABEL: uabd_8b: |
| 195 | +; CHECK: // %bb.0: |
| 196 | +; CHECK-NEXT: uabd v0.8b, v0.8b, v1.8b |
| 197 | +; CHECK-NEXT: ret |
| 198 | + %a.zext = zext <8 x i8> %a to <8 x i16> |
| 199 | + %b.zext = zext <8 x i8> %b to <8 x i16> |
| 200 | + %sub = sub <8 x i16> %a.zext, %b.zext |
| 201 | + %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) |
| 202 | + %trunc = trunc <8 x i16> %abs to <8 x i8> |
| 203 | + ret <8 x i8> %trunc |
| 204 | +} |
| 205 | + |
| 206 | +define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) #0 { |
| 207 | +; CHECK-LABEL: uabd_16b: |
| 208 | +; CHECK: // %bb.0: |
| 209 | +; CHECK-NEXT: uabd v0.16b, v0.16b, v1.16b |
| 210 | +; CHECK-NEXT: ret |
| 211 | + %a.zext = zext <16 x i8> %a to <16 x i16> |
| 212 | + %b.zext = zext <16 x i8> %b to <16 x i16> |
| 213 | + %sub = sub <16 x i16> %a.zext, %b.zext |
| 214 | + %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true) |
| 215 | + %trunc = trunc <16 x i16> %abs to <16 x i8> |
| 216 | + ret <16 x i8> %trunc |
| 217 | +} |
| 218 | + |
| 219 | +define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) #0 { |
| 220 | +; CHECK-LABEL: uabd_4h: |
| 221 | +; CHECK: // %bb.0: |
| 222 | +; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h |
| 223 | +; CHECK-NEXT: ret |
| 224 | + %a.zext = zext <4 x i16> %a to <4 x i32> |
| 225 | + %b.zext = zext <4 x i16> %b to <4 x i32> |
| 226 | + %sub = sub <4 x i32> %a.zext, %b.zext |
| 227 | + %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) |
| 228 | + %trunc = trunc <4 x i32> %abs to <4 x i16> |
| 229 | + ret <4 x i16> %trunc |
| 230 | +} |
| 231 | + |
| 232 | +define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) #0 { |
| 233 | +; CHECK-LABEL: uabd_4h_promoted_ops: |
| 234 | +; CHECK: // %bb.0: |
| 235 | +; CHECK-NEXT: bic v0.4h, #255, lsl #8 |
| 236 | +; CHECK-NEXT: bic v1.4h, #255, lsl #8 |
| 237 | +; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h |
| 238 | +; CHECK-NEXT: abs v0.4h, v0.4h |
| 239 | +; CHECK-NEXT: ret |
| 240 | + %a.zext = zext <4 x i8> %a to <4 x i16> |
| 241 | + %b.zext = zext <4 x i8> %b to <4 x i16> |
| 242 | + %sub = sub <4 x i16> %a.zext, %b.zext |
| 243 | + %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true) |
| 244 | + ret <4 x i16> %abs |
| 245 | +} |
| 246 | + |
| 247 | +define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) #0 { |
| 248 | +; CHECK-LABEL: uabd_8h: |
| 249 | +; CHECK: // %bb.0: |
| 250 | +; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h |
| 251 | +; CHECK-NEXT: ret |
| 252 | + %a.zext = zext <8 x i16> %a to <8 x i32> |
| 253 | + %b.zext = zext <8 x i16> %b to <8 x i32> |
| 254 | + %sub = sub <8 x i32> %a.zext, %b.zext |
| 255 | + %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true) |
| 256 | + %trunc = trunc <8 x i32> %abs to <8 x i16> |
| 257 | + ret <8 x i16> %trunc |
| 258 | +} |
| 259 | + |
| 260 | +define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) #0 { |
| 261 | +; CHECK-LABEL: uabd_8h_promoted_ops: |
| 262 | +; CHECK: // %bb.0: |
| 263 | +; CHECK-NEXT: uabdl v0.8h, v0.8b, v1.8b |
| 264 | +; CHECK-NEXT: ret |
| 265 | + %a.zext = zext <8 x i8> %a to <8 x i16> |
| 266 | + %b.zext = zext <8 x i8> %b to <8 x i16> |
| 267 | + %sub = sub <8 x i16> %a.zext, %b.zext |
| 268 | + %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) |
| 269 | + ret <8 x i16> %abs |
| 270 | +} |
| 271 | + |
| 272 | +define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) #0 { |
| 273 | +; CHECK-LABEL: uabd_2s: |
| 274 | +; CHECK: // %bb.0: |
| 275 | +; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s |
| 276 | +; CHECK-NEXT: ret |
| 277 | + %a.zext = zext <2 x i32> %a to <2 x i64> |
| 278 | + %b.zext = zext <2 x i32> %b to <2 x i64> |
| 279 | + %sub = sub <2 x i64> %a.zext, %b.zext |
| 280 | + %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) |
| 281 | + %trunc = trunc <2 x i64> %abs to <2 x i32> |
| 282 | + ret <2 x i32> %trunc |
| 283 | +} |
| 284 | + |
| 285 | +define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) #0 { |
| 286 | +; CHECK-LABEL: uabd_2s_promoted_ops: |
| 287 | +; CHECK: // %bb.0: |
| 288 | +; CHECK-NEXT: movi d2, #0x00ffff0000ffff |
| 289 | +; CHECK-NEXT: and v0.8b, v0.8b, v2.8b |
| 290 | +; CHECK-NEXT: and v1.8b, v1.8b, v2.8b |
| 291 | +; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s |
| 292 | +; CHECK-NEXT: abs v0.2s, v0.2s |
| 293 | +; CHECK-NEXT: ret |
| 294 | + %a.zext = zext <2 x i16> %a to <2 x i32> |
| 295 | + %b.zext = zext <2 x i16> %b to <2 x i32> |
| 296 | + %sub = sub <2 x i32> %a.zext, %b.zext |
| 297 | + %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true) |
| 298 | + ret <2 x i32> %abs |
| 299 | +} |
| 300 | + |
| 301 | +define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) #0 { |
| 302 | +; CHECK-LABEL: uabd_4s: |
| 303 | +; CHECK: // %bb.0: |
| 304 | +; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s |
| 305 | +; CHECK-NEXT: ret |
| 306 | + %a.zext = zext <4 x i32> %a to <4 x i64> |
| 307 | + %b.zext = zext <4 x i32> %b to <4 x i64> |
| 308 | + %sub = sub <4 x i64> %a.zext, %b.zext |
| 309 | + %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true) |
| 310 | + %trunc = trunc <4 x i64> %abs to <4 x i32> |
| 311 | + ret <4 x i32> %trunc |
| 312 | +} |
| 313 | + |
| 314 | +define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) #0 { |
| 315 | +; CHECK-LABEL: uabd_4s_promoted_ops: |
| 316 | +; CHECK: // %bb.0: |
| 317 | +; CHECK-NEXT: uabdl v0.4s, v0.4h, v1.4h |
| 318 | +; CHECK-NEXT: ret |
| 319 | + %a.zext = zext <4 x i16> %a to <4 x i32> |
| 320 | + %b.zext = zext <4 x i16> %b to <4 x i32> |
| 321 | + %sub = sub <4 x i32> %a.zext, %b.zext |
| 322 | + %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) |
| 323 | + ret <4 x i32> %abs |
| 324 | +} |
| 325 | + |
| 326 | +define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) #0 { |
| 327 | +; CHECK-LABEL: uabd_2d: |
| 328 | +; CHECK: // %bb.0: |
| 329 | +; CHECK-NEXT: mov x8, v0.d[1] |
| 330 | +; CHECK-NEXT: fmov x10, d0 |
| 331 | +; CHECK-NEXT: mov x9, v1.d[1] |
| 332 | +; CHECK-NEXT: subs x8, x8, x9 |
| 333 | +; CHECK-NEXT: fmov x9, d1 |
| 334 | +; CHECK-NEXT: ngcs x11, xzr |
| 335 | +; CHECK-NEXT: subs x9, x10, x9 |
| 336 | +; CHECK-NEXT: ngcs x10, xzr |
| 337 | +; CHECK-NEXT: cmp x10, #0 |
| 338 | +; CHECK-NEXT: cneg x9, x9, lt |
| 339 | +; CHECK-NEXT: cmp x11, #0 |
| 340 | +; CHECK-NEXT: cneg x8, x8, lt |
| 341 | +; CHECK-NEXT: fmov d0, x9 |
| 342 | +; CHECK-NEXT: fmov d1, x8 |
| 343 | +; CHECK-NEXT: mov v0.d[1], v1.d[0] |
| 344 | +; CHECK-NEXT: ret |
| 345 | + %a.zext = zext <2 x i64> %a to <2 x i128> |
| 346 | + %b.zext = zext <2 x i64> %b to <2 x i128> |
| 347 | + %sub = sub <2 x i128> %a.zext, %b.zext |
| 348 | + %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true) |
| 349 | + %trunc = trunc <2 x i128> %abs to <2 x i64> |
| 350 | + ret <2 x i64> %trunc |
| 351 | +} |
| 352 | + |
| 353 | +define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) #0 { |
| 354 | +; CHECK-LABEL: uabd_2d_promoted_ops: |
| 355 | +; CHECK: // %bb.0: |
| 356 | +; CHECK-NEXT: uabdl v0.2d, v0.2s, v1.2s |
| 357 | +; CHECK-NEXT: ret |
| 358 | + %a.zext = zext <2 x i32> %a to <2 x i64> |
| 359 | + %b.zext = zext <2 x i32> %b to <2 x i64> |
| 360 | + %sub = sub <2 x i64> %a.zext, %b.zext |
| 361 | + %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) |
| 362 | + ret <2 x i64> %abs |
| 363 | +} |
| 364 | + |
| 365 | +declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1) |
| 366 | +declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1) |
| 367 | + |
| 368 | +declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1) |
| 369 | +declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1) |
| 370 | +declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1) |
| 371 | + |
| 372 | +declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1) |
| 373 | +declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1) |
| 374 | +declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1) |
| 375 | + |
| 376 | +declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1) |
| 377 | +declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1) |
| 378 | + |
| 379 | +declare <2 x i128> @llvm.abs.v2i128(<2 x i128>, i1) |
| 380 | + |
| 381 | +attributes #0 = { "target-features"="+neon" } |
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