[VE] Fix several conflicts against upstream

kaz7 · kaz7 · commit dacf3069ea6b · 2022-03-28T09:21:57.000+09:00
diff --git a/clang/include/clang/Basic/BuiltinsVE.def b/clang/include/clang/Basic/BuiltinsVE.def
@@ -11,7 +11,11 @@
 //
 //===----------------------------------------------------------------------===//
 
-// The format of this database matches clang/Basic/Builtins.def.
+#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
+#   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
+#endif
+
+// The format of this database is decribed in clang/Basic/Builtins.def.
 
 BUILTIN(__builtin_ve_vl_pack_f32p, "ULifC*fC*", "n")
 BUILTIN(__builtin_ve_vl_pack_f32a, "ULifC*", "n")
@@ -21,6 +25,8 @@ BUILTIN(__builtin_ve_vl_extract_vm512l, "V256bV512b", "n")
 BUILTIN(__builtin_ve_vl_insert_vm512u, "V512bV512bV256b", "n")
 BUILTIN(__builtin_ve_vl_insert_vm512l, "V512bV512bV256b", "n")
 
+// Use generated BUILTIN definitions
 #include "clang/Basic/BuiltinsVEVL.gen.def"
 
 #undef BUILTIN
+#undef TARGET_BUILTIN
diff --git a/clang/include/clang/module.modulemap b/clang/include/clang/module.modulemap
@@ -56,7 +56,6 @@ module Clang_Basic {
   textual header "Basic/BuiltinsX86.def"
   textual header "Basic/BuiltinsX86_64.def"
   textual header "Basic/BuiltinsXCore.def"
-  textual header "Basic/BuiltinsVE.def"
   textual header "Basic/CodeGenOptions.def"
   textual header "Basic/DiagnosticOptions.def"
   textual header "Basic/Features.def"
diff --git a/clang/lib/Basic/Targets/VE.cpp b/clang/lib/Basic/Targets/VE.cpp
@@ -21,8 +21,6 @@ using namespace clang::targets;
 const Builtin::Info VETargetInfo::BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
-#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
-  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
 #include "clang/Basic/BuiltinsVE.def"
 };
 
diff --git a/clang/lib/Basic/Targets/VE.h b/clang/lib/Basic/Targets/VE.h
@@ -76,25 +76,25 @@ class LLVM_LIBRARY_VISIBILITY VETargetInfo : public TargetInfo {
 
   ArrayRef<const char *> getGCCRegNames() const override {
     static const char *const GCCRegNames[] = {
-      // Regular registers
+        // Regular registers
         "sx0",  "sx1",  "sx2",  "sx3",  "sx4",  "sx5",  "sx6",  "sx7",
-        "sx8",  "sx9", "sx10", "sx11", "sx12", "sx13", "sx14", "sx15",
-       "sx16", "sx17", "sx18", "sx19", "sx20", "sx21", "sx22", "sx23",
-       "sx24", "sx25", "sx26", "sx27", "sx28", "sx29", "sx30", "sx31",
-       "sx32", "sx33", "sx34", "sx35", "sx36", "sx37", "sx38", "sx39",
-       "sx40", "sx41", "sx42", "sx43", "sx44", "sx45", "sx46", "sx47",
-       "sx48", "sx49", "sx50", "sx51", "sx52", "sx53", "sx54", "sx55",
-       "sx56", "sx57", "sx58", "sx59", "sx60", "sx61", "sx62", "sx63",
-      // Vector registers
+        "sx8",  "sx9",  "sx10", "sx11", "sx12", "sx13", "sx14", "sx15",
+        "sx16", "sx17", "sx18", "sx19", "sx20", "sx21", "sx22", "sx23",
+        "sx24", "sx25", "sx26", "sx27", "sx28", "sx29", "sx30", "sx31",
+        "sx32", "sx33", "sx34", "sx35", "sx36", "sx37", "sx38", "sx39",
+        "sx40", "sx41", "sx42", "sx43", "sx44", "sx45", "sx46", "sx47",
+        "sx48", "sx49", "sx50", "sx51", "sx52", "sx53", "sx54", "sx55",
+        "sx56", "sx57", "sx58", "sx59", "sx60", "sx61", "sx62", "sx63",
+        // Vector registers
         "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
         "v8",  "v9", "v10", "v11", "v12", "v13", "v14", "v15",
-       "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
-       "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
-       "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
-       "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
-       "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
-       "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
-      // Special registers
+        "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+        "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+        "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
+        "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
+        "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
+        "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
+        // Special registers
         "vl",  "vixr",  "ucc", "psw", "sar", "pmmr",
         "pmcr0", "pmcr1", "pmcr2", "pmcr3",
         "pmc0", "pmc1", "pmc2", "pmc3", "pmc4", "pmc5", "pmc6", "pmc7",
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1465,8 +1465,6 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
 #endif
   }
 
-
-
   // Add system include arguments for all targets but IAMCU.
   if (!IsIAMCU)
     forAllAssociatedToolChains(C, JA, getToolChain(),
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
@@ -12591,8 +12591,6 @@ QualType Sema::GetSignedVectorType(QualType V) {
     return Context.getExtVectorType(Context.LongLongTy, VTy->getNumElements());
   }
 
-  if (VTy->isExtVectorBoolType())
-    return Context.getExtVectorType(Context.BoolTy, VTy->getNumElements());
   if (TypeSize == Context.getTypeSize(Context.Int128Ty))
     return Context.getVectorType(Context.Int128Ty, VTy->getNumElements(),
                                  VectorType::GenericVector);
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
@@ -6111,6 +6111,7 @@ QualType Sema::CheckVectorConditionalTypes(ExprResult &Cond, ExprResult &LHS,
 
   QualType ResultType;
 
+
   if (LHSVT && RHSVT) {
     if (isa<ExtVectorType>(CondVT) != isa<ExtVectorType>(LHSVT)) {
       Diag(QuestionLoc, diag::err_conditional_vector_cond_result_mismatch)
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
@@ -1409,7 +1409,6 @@ def int_vp_scatter: DefaultAttrsIntrinsic<[],
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty],
                               [ IntrArgMemOnly, IntrNoSync, IntrWillReturn ]>; // TODO allow IntrNoCapture for vectors of pointers
-// TODO allow IntrNoCapture for vectors of pointers
 
 // Experimental strided memory accesses
 def int_experimental_vp_strided_store : DefaultAttrsIntrinsic<[],
@@ -2140,6 +2139,6 @@ include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsAMDGPU.td"
 include "llvm/IR/IntrinsicsBPF.td"
 include "llvm/IR/IntrinsicsSystemZ.td"
-include "llvm/IR/IntrinsicsVE.td"
 include "llvm/IR/IntrinsicsWebAssembly.td"
 include "llvm/IR/IntrinsicsRISCV.td"
+include "llvm/IR/IntrinsicsVE.td"
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
@@ -157,7 +157,7 @@ void initializeEntryExitInstrumenterPass(PassRegistry&);
 void initializeExpandMemCmpPassPass(PassRegistry&);
 void initializeExpandPostRAPass(PassRegistry&);
 void initializeExpandReductionsPass(PassRegistry&);
-void initializeExpandVectorPredicationPass(PassRegistry&);
+void initializeExpandVectorPredicationPass(PassRegistry &);
 void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&);
 void initializeExternalAAWrapperPassPass(PassRegistry&);
 void initializeFEntryInserterPass(PassRegistry&);
diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h
@@ -35,12 +35,6 @@ void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
 } // namespace llvm
 
 namespace llvm {
-
-/// Target Constants {
-const unsigned StandardVectorWidth = 256;
-const unsigned PackedVectorWidth = 512;
-/// } Target Constants
-
 // Enums corresponding to VE condition codes, both icc's and fcc's.  These
 // values must be kept in sync with the ones in the .td file.
 namespace VECC {
@@ -418,5 +412,8 @@ inline static uint64_t mimm2Val(uint64_t Val) {
 inline unsigned M0(unsigned Val) { return Val + 64; }
 inline unsigned M1(unsigned Val) { return Val; }
 
+static const unsigned StandardVectorWidth = 256;
+static const unsigned PackedVectorWidth = 512;
+
 } // namespace llvm
 #endif
diff --git a/llvm/lib/Target/VE/VECustomDAG.cpp b/llvm/lib/Target/VE/VECustomDAG.cpp
@@ -20,7 +20,7 @@
 #include "llvm/CodeGen/TargetLowering.h"
 
 #ifndef DEBUG_TYPE
-#define DEBUG_TYPE "customdag"
+#define DEBUG_TYPE "vecustomdag"
 #endif
 
 namespace llvm {
diff --git a/llvm/lib/Target/VE/VECustomDAG.h b/llvm/lib/Target/VE/VECustomDAG.h
@@ -1,13 +1,13 @@
-//===-- VECustomDAG.h - VE Custom DAG Nodes ------------*- C++ -*-===//
+//===------------ VECustomDAG.h - VE Custom DAG Nodes -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines the interfaces that VE uses to lower LLVM code into a
-// selection DAG.
+// This file defines the helper functions that VE uses to lower LLVM code into a
+// selection DAG.  For example, hiding SDLoc, and easy to use SDNodeFlags.
 //
 //===----------------------------------------------------------------------===//
 
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -238,7 +238,6 @@ bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
     return false;
   }
   if (matchADDRrr(Addr, LHS, RHS)) {
-    // Move a frameiindex to LHS:
     // If the input is a pair of a frame-index and a register, move a
     // frame-index to LHS.  This generates MI with following operands.
     //    %dest, #FI, %reg, offset
@@ -399,43 +398,41 @@ void VEDAGToDAGISel::Select(SDNode *N) {
   }
 
   switch (N->getOpcode()) {
-  default:
-    break;
+
+  // Late eliminate the LEGALAVL wrapper
+  case VEISD::LEGALAVL:
+    ReplaceNode(N, N->getOperand(0).getNode());
+    return;
 
   // Lower (broadcast 1) and (broadcast 0) to VM[P]0
   case VEISD::VEC_BROADCAST: {
     MVT SplatResTy = N->getSimpleValueType(0);
     if (SplatResTy.getVectorElementType() != MVT::i1)
       break;
 
-    // broadcasting true?
+    // Constant non-zero broadcast.
     auto BConst = dyn_cast<ConstantSDNode>(N->getOperand(0));
     if (!BConst)
       break;
     bool BCTrueMask = (BConst->getSExtValue() != 0);
     if (!BCTrueMask)
       break;
 
-    // Decode the register
+    // Packed or non-packed.
     SDValue New;
-    if (SplatResTy.getVectorNumElements() == 256) {
+    if (SplatResTy.getVectorNumElements() == StandardVectorWidth) {
       New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(N), VE::VM0,
                                    MVT::v256i1);
-    } else if (SplatResTy.getVectorNumElements() == 512) {
+    } else if (SplatResTy.getVectorNumElements() == PackedVectorWidth) {
       New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(N), VE::VMP0,
                                    MVT::v512i1);
     } else
       break;
 
-    // ok replace
+    // Replace.
     ReplaceNode(N, New.getNode());
-     return;
-   }
-
-  // Late eliminate the LEGALAVL wrapper
-  case VEISD::LEGALAVL:
-    ReplaceNode(N, N->getOperand(0).getNode());
     return;
+  }
 
   case VEISD::GLOBAL_BASE_REG:
     ReplaceNode(N, getGlobalBaseReg());
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -16,16 +16,16 @@ def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
 
 // The extract/insert patterns.
 def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
-          (v256i1 (EXTRACT_SUBREG v512i1:$vm, sub_vm_even))>;
+          (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>;
 
 def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
-          (v256i1 (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd))>;
+          (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>;
 
 def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
-          (v512i1 (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even))>;
+          (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>;
 
 def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
-          (v512i1 (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd))>;
+          (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
 
 // VMRG patterns.
 def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
diff --git a/llvm/lib/Target/VE/VEInstrPatternsVec.td b/llvm/lib/Target/VE/VEInstrPatternsVec.td
@@ -1,6 +1,14 @@
+//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
 //===----------------------------------------------------------------------===//
-// Vector Instruction Patterns for non vectorize subtarget which supports
-// intrinsics and v256f64 vector regisetr only.
+//
+// This file describes the VEC_* prefixed intermediate SDNodes and their
+// isel patterns.
+//
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
@@ -167,16 +167,6 @@ tablegen("IntrinsicsXCore") {
   td_file = "Intrinsics.td"
 }
 
-tablegen("IntrinsicsVE") {
-  visibility = [ ":public_tablegen" ]
-  output_name = "IntrinsicsVE.h"
-  args = [
-    "-gen-intrinsic-enums",
-    "-intrinsic-prefix=ve",
-  ]
-  td_file = "Intrinsics.td"
-}
-
 # Groups all tablegen() calls that create .inc files that are included in
 # IR's public headers.  //llvm/lib/IR has this as a public_dep, so targets
 # depending on //llvm/lib/IR don't need to depend on this.  This exists
@@ -206,6 +196,5 @@ group("public_tablegen") {
     ":IntrinsicsWebAssembly",
     ":IntrinsicsX86",
     ":IntrinsicsXCore",
-    ":IntrinsicsVE",
   ]
 }
diff --git a/llvm/utils/vscode/llvm/package-lock.json b/llvm/utils/vscode/llvm/package-lock.json

Original file line number	Diff line number	Diff line change
`@@ -1465,8 +1465,6 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,`
`1465`	`1465`	`#endif`
`1466`	`1466`	`}`
`1467`	`1467`
`1468`		`-`
`1469`		`-`
`1470`	`1468`	`// Add system include arguments for all targets but IAMCU.`
`1471`	`1469`	`if (!IsIAMCU)`
`1472`	`1470`	`forAllAssociatedToolChains(C, JA, getToolChain(),`
Original file line number	Diff line number	Diff line change
`@@ -12591,8 +12591,6 @@ QualType Sema::GetSignedVectorType(QualType V) {`
`12591`	`12591`	`return Context.getExtVectorType(Context.LongLongTy, VTy->getNumElements());`
`12592`	`12592`	`}`
`12593`	`12593`
`12594`		`- if (VTy->isExtVectorBoolType())`
`12595`		`- return Context.getExtVectorType(Context.BoolTy, VTy->getNumElements());`
`12596`	`12594`	`if (TypeSize == Context.getTypeSize(Context.Int128Ty))`
`12597`	`12595`	`return Context.getVectorType(Context.Int128Ty, VTy->getNumElements(),`
`12598`	`12596`	`VectorType::GenericVector);`