Merge commit 'ae1bb44ed80b7b60c3fd2426c8bee3df93e4a314' into merge/ve-setcc

Author: Simon Moll

llvm/lib/Target/VE/VVPInstrInfo.td

@@ -73,11 +73,20 @@ def SDTSelectVVP : SDTypeProfile<1, 4, [       // vp_select, vp_merge
   IsVLVT<4>
 ]>;
 
-// setcc (lhs, rhs, cc, mask, vl)
+// SetCC (lhs, rhs, cc, mask, vl)
 def SDTSetCCVVP : SDTypeProfile<1, 5, [        // vp_setcc
-  SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>, SDTCisInt<4>, SDTCisSameNumEltsAs<0, 4>, IsVLVT<5>
+  SDTCisVec<0>,
+  SDTCisVec<1>,
+  SDTCisSameNumEltsAs<0, 1>,
+  SDTCisSameAs<1, 2>,
+  SDTCisVT<3, OtherVT>,
+  SDTCisInt<4>,
+  SDTCisSameNumEltsAs<0, 4>,
+  IsVLVT<5>
 ]>;
 
+
+
 // s/uint_to_fp
 def SDTIntToFPOpVVP : SDTypeProfile<1, 3, [    // [su]int_to_fp
   SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisSameNumEltsAs<0, 2>, IsVLVT<3>
@@ -245,3 +254,5 @@ def c_vvp_fmaxnum     : vvp_commutative<vvp_fmaxnum>;
 def c_vvp_ffma        : vvp_fma_commutative<vvp_ffma>;
 def c_vvp_ffms        : vvp_fma_commutative<vvp_ffms>;
 def c_vvp_ffmsn       : vvp_fma_commutative<vvp_ffmsn>;
+
+// } Binary Operators

llvm/lib/Target/VE/VVPInstrPatternsVec.td

@@ -499,42 +499,38 @@ defm : Merge_mvv_ShortLong<vvp_select,
                            v256i64,
                            v256i32, "VMRG">;
 
-multiclass VectorSelect_Packed<ValueType PackedVT> {
-    def : Pat<(PackedVT (vvp_select PackedVT:$vtrue, PackedVT:$vfalse, v512i1:$vm, i32:$pivot)),
-                        (VMRGWvvml_v $vfalse, $vtrue, $vm, $pivot, $vfalse)>;
-}
-
-defm : VectorSelect_Packed<v512i32>;
-defm : VectorSelect_Packed<v512f32>;
+defm : Merge_mvv<vvp_select,v512i32,v512i1,"VMRGW">;
+defm : Merge_mvv<vvp_select,v512f32,v512i1,"VMRGW">;
 
 
 ///// Comparison (VVP_SETCC) /////
 
-multiclass Set_CC<ValueType MaskVT, ValueType DataVT, string FmkBaseName, string CmpBaseName, SDPatternOperator CCMatcher, SDPatternOperator CCConv, string MaskTag="m"> {
-  // TODO: Fused broadcast. Requires adapting SPU reg type to element type (as done for PVFADDUP, etc).
-  // TODO: Predicate inversion to fuse broadcast (may do this in cpp code).
-  // // Unmasked + broadcast
-  // def : Pat<(MaskVT (vvp_setcc (any_broadcast ScalarVT:$LHS), DataVT:$RHS, CCMatcher:$cond, (MaskVT true_mask), i32:$vl)),
-  //                   (!cast<Instruction>(FmkBaseName#"vl") (CCConv $cond), (!cast<Instruction>(CmpBaseName#"rvl") $LHS, $RHS, $vl), $vl)>;
-  // unmasked
-  def : Pat<(MaskVT (vvp_setcc DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, (MaskVT true_mask), i32:$vl)),
-                    (!cast<Instruction>(FmkBaseName#"vl") (CCConv $cond), (!cast<Instruction>(CmpBaseName#"vvl") $LHS, $RHS, $vl), $vl)>;
-  // masked
-  def : Pat<(MaskVT (vvp_setcc DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, MaskVT:$vm, i32:$vl)),
-                    (!cast<Instruction>(FmkBaseName#"v"#MaskTag#"l") (CCConv $cond), (!cast<Instruction>(CmpBaseName#"vvl") $LHS, $RHS, $vl), $vm, $vl)>;
-}
-
-multiclass Set_CC_256<ValueType DataVT, string FmkBaseName, string CmpBaseName, SDPatternOperator CCMatcher, SDNodeXForm CCConv>
-  : Set_CC<v256i1, DataVT, FmkBaseName, CmpBaseName, CCMatcher, CCConv, "m">;
-
-// SETCC (256)
-defm : Set_CC_256<v256i64,"VFMKL","VCMPUL",CCUIOp,icond2cc>;
-defm : Set_CC_256<v256i64,"VFMKL","VCMPSL",CCSIOp,icond2cc>;
-defm : Set_CC_256<v256f64,"VFMKL","VFCMPD",cond,fcond2cc>;
-
-defm : Set_CC_256<v256i32,"VFMKW","VCMPUW",CCUIOp,icond2cc>;
-defm : Set_CC_256<v256i32,"VFMKW","VCMPSWZX",CCSIOp,icond2cc>;
-defm : Set_CC_256<v256f32,"VFMKS","VFCMPS",cond,fcond2cc>;
+multiclass Set_CC<ValueType DataVT, string FmkBaseName, string CmpBaseName, SDPatternOperator CCMatcher, SDNodeXForm CCConv> {
+  // Unmasked.
+  def : Pat<(v256i1 (vvp_setcc
+              DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, (v256i1 true_mask), i32:$vl)),
+              (!cast<Instruction>(FmkBaseName#"vl")
+                (CCConv $cond),
+                (!cast<Instruction>(CmpBaseName#"vvl")
+                  $LHS, $RHS, $vl),
+                $vl)>;
+  // Masked.
+  def : Pat<(v256i1 (vvp_setcc
+              DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, v256i1:$vm, i32:$vl)),
+              (!cast<Instruction>(FmkBaseName#"vml")
+                (CCConv $cond),
+                (!cast<Instruction>(CmpBaseName#"vvl")
+                  $LHS, $RHS, $vl),
+                $vm, $vl)>;
+}
+
+defm : Set_CC<v256i64,"VFMKL","VCMPUL",CCUIOp,icond2cc>;
+defm : Set_CC<v256i64,"VFMKL","VCMPSL",CCSIOp,icond2cc>;
+defm : Set_CC<v256f64,"VFMKL","VFCMPD",cond,fcond2cc>;
+
+defm : Set_CC<v256i32,"VFMKW","VCMPUW",CCUIOp,icond2cc>;
+defm : Set_CC<v256i32,"VFMKW","VCMPSWZX",CCSIOp,icond2cc>;
+defm : Set_CC<v256f32,"VFMKS","VFCMPS",cond,fcond2cc>;
 
 ///// Conversion /////
 

llvm/lib/Target/VE/VVPNodes.def

@@ -159,8 +159,12 @@ REGISTER_TERNARY_VVP_OP(VVP_FFMS) REGISTER_PACKED(VVP_FFMS)
 REGISTER_TERNARY_VVP_OP(VVP_FFMSN) REGISTER_PACKED(VVP_FFMSN)
 
 // Select
-ADD_TERNARY_VVP_OP(VVP_SELECT,VSELECT) HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT)  REGISTER_PACKED(VVP_SELECT)
+ADD_TERNARY_VVP_OP(VVP_SELECT,VSELECT)  REGISTER_PACKED(VVP_SELECT)
+
+// Shuffles.
+HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT)
 HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT)
+
 ADD_TERNARY_VVP_OP(VVP_SETCC,SETCC) HANDLE_VP_TO_VVP(VP_SETCC, VVP_SETCC) 
 
 // sint <> fp