Merge pull request #143 from sx-aurora-dev/merge/ve-custom-dag

Merge/ve custom dag

Author: kaz7

llvm/lib/Target/VE/CMakeLists.txt

@@ -15,11 +15,11 @@ tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
 add_public_tablegen_target(VECommonTableGen)
 
 add_llvm_target(VECodeGen
-  CustomDAG.cpp
   LVLGen.cpp
   MaskView.cpp
   ShuffleSynthesis.cpp
   VEAsmPrinter.cpp
+  VECustomDAG.cpp
   VEFrameLowering.cpp
   VEISelDAGToDAG.cpp
   VEISelLowering.cpp

llvm/lib/Target/VE/MaskView.cpp

@@ -1,4 +1,4 @@
-#include "CustomDAG.h"
+#include "VECustomDAG.h"
 #include "MaskView.h"
 
 #define DEBUG_TYPE "ve-maskview"
@@ -98,7 +98,7 @@ struct ExtractSubvectorView : public MaskView {
   virtual SDNode *getNode() const override { return EVN.getNode(); }
 };
 
-static SplitView splitBuildVector(BuildVectorSDNode &BVN, CustomDAG &CDAG) {
+static SplitView splitBuildVector(BuildVectorSDNode &BVN, VECustomDAG &CDAG) {
   std::vector<SDValue> Inputs[2];
 
   for (unsigned Idx = 0; Idx < BVN.getNumOperands(); ++Idx) {
@@ -163,7 +163,7 @@ struct SynthShuffle : public MaskView {
   virtual unsigned getNumElements() const override { return Mask.size(); }
 };
 
-static SplitView splitShuffleVector(ShuffleVectorSDNode &SVN, CustomDAG &CDAG) {
+static SplitView splitShuffleVector(ShuffleVectorSDNode &SVN, VECustomDAG &CDAG) {
   EVT OrigVT = SVN.getValueType(0);
   EVT LegalResVT = CDAG.legalizeVectorType(SDValue(&SVN, 0),
                                            VVPExpansionMode::ToNativeWidth);
@@ -231,7 +231,7 @@ static SplitView splitShuffleVector(ShuffleVectorSDNode &SVN, CustomDAG &CDAG) {
   return Split;
 }
 
-SplitView requestSplitView(SDNode *N, CustomDAG &CDAG) {
+SplitView requestSplitView(SDNode *N, VECustomDAG &CDAG) {
   auto BVN = dyn_cast<BuildVectorSDNode>(N);
   if (BVN)
     return splitBuildVector(*BVN, CDAG);

llvm/lib/Target/VE/MaskView.h

@@ -6,7 +6,7 @@
 
 namespace llvm {
 
-struct CustomDAG;
+struct VECustomDAG;
 
 struct ElemSelect {
   SDValue V;          // the value that is chosen
@@ -79,7 +79,7 @@ struct SplitView {
   bool isValid() const { return LoView && HiView; }
 };
 
-SplitView requestSplitView(SDNode *N, CustomDAG &CDAG);
+SplitView requestSplitView(SDNode *N, VECustomDAG &CDAG);
 
 MaskView *requestMaskView(SDNode *N);
 

llvm/lib/Target/VE/ShuffleSynthesis.cpp

@@ -21,7 +21,7 @@ class ZeroDefaultingView : public MaskView {
   ElemSelect ZeroInsert;
 
 public:
-  ZeroDefaultingView(MaskView &BaseMV, CustomDAG &CDAG)
+  ZeroDefaultingView(MaskView &BaseMV, VECustomDAG &CDAG)
       : BaseMV(BaseMV), ConstZeroV(CDAG.getConstant(0, MVT::i32)),
         ZeroInsert(ConstZeroV) {}
 };
@@ -30,7 +30,7 @@ class ZeroDefaultingView : public MaskView {
 // or vector registers
 class VRegView final : public ZeroDefaultingView {
 public:
-  VRegView(CustomDAG &CDAG, MaskView &BitMV)
+  VRegView(VECustomDAG &CDAG, MaskView &BitMV)
       : ZeroDefaultingView(BitMV, CDAG) {}
 
   ~VRegView() {}
@@ -74,7 +74,7 @@ class VRegView final : public ZeroDefaultingView {
 
 class BitMaskView final : public ZeroDefaultingView {
 public:
-  BitMaskView(MaskView &BitMV, CustomDAG &CDAG)
+  BitMaskView(MaskView &BitMV, VECustomDAG &CDAG)
       : ZeroDefaultingView(BitMV, CDAG) {}
   ~BitMaskView() {}
 
@@ -231,7 +231,7 @@ static bool AnalyzeReversal(BitMaskView &BitMV, unsigned DestPartBase,
 
 // match a 64 bit segment, mapping out all source bits
 // FIXME this implies knowledge about the underlying object structure
-MaskShuffleAnalysis::MaskShuffleAnalysis(MaskView &MV, CustomDAG &CDAG)
+MaskShuffleAnalysis::MaskShuffleAnalysis(MaskView &MV, VECustomDAG &CDAG)
     : MV(MV) {
   // This view only reflects insertions of actual i1 bits (from other mask
   // registers, or MVT::i32 constants). Insertion of SX register will be masked out.
@@ -290,7 +290,7 @@ MaskShuffleAnalysis::MaskShuffleAnalysis(MaskView &MV, CustomDAG &CDAG)
 }
 
 SDValue MaskShuffleAnalysis::synthesize(SDValue Passthru, BitSelect &BSel,
-                                        SDValue SXV, CustomDAG &CDAG) const {
+                                        SDValue SXV, VECustomDAG &CDAG) const {
   const uint64_t AllSetMask = (uint64_t)-1;
 
   // match full register copies
@@ -353,7 +353,7 @@ bool MaskShuffleAnalysis::analyzeVectorSources(bool &AllTrue) const {
 }
 
 // materialize the code to synthesize this operation
-SDValue MaskShuffleAnalysis::synthesize(CustomDAG &CDAG, EVT LegalMaskVT) {
+SDValue MaskShuffleAnalysis::synthesize(VECustomDAG &CDAG, EVT LegalMaskVT) {
   Packing PackFlag =
       isPackedType(LegalMaskVT) ? Packing::Dense : Packing::Normal;
 
@@ -504,7 +504,7 @@ struct ScalarTransferOp final : public AbstractShuffleOp {
   virtual ~ScalarTransferOp() {}
 
   // transfer all insert positions to their destination
-  virtual SDValue synthesize(MaskView &MV, CustomDAG &CDAG,
+  virtual SDValue synthesize(MaskView &MV, VECustomDAG &CDAG,
                              SDValue PartialV) override {
     SDValue AccuV = PartialV;
 
@@ -584,7 +584,7 @@ struct VMVShuffleOp final : public AbstractShuffleOp {
   unsigned getAVL() const { return DestStartPos + SubVectorLength; }
 
   // transfer all insert positions to their destination
-  SDValue synthesize(MaskView &MV, CustomDAG &CDAG, SDValue PartialV) override {
+  SDValue synthesize(MaskView &MV, VECustomDAG &CDAG, SDValue PartialV) override {
     // noop VMV
     if (ShiftAmount == 0 && PartialV->isUndef())
       return SrcVector;
@@ -737,7 +737,7 @@ struct PatternShuffleOp final : public AbstractShuffleOp {
   }
 
   // transfer all insert positions to their destination
-  SDValue synthesize(MaskView &MV, CustomDAG &CDAG, SDValue PartialV) override {
+  SDValue synthesize(MaskView &MV, VECustomDAG &CDAG, SDValue PartialV) override {
     EVT LegalResVT =
         PartialV.getValueType(); // LegalizeVectorType(Op.getValueType(),
                                  // Op, DAG, Mode);
@@ -902,7 +902,7 @@ struct BroadcastOp final : public AbstractShuffleOp {
 
   ~BroadcastOp() {}
 
-  SDValue synthesize(MaskView &MV, CustomDAG &CDAG, SDValue PartialV) override {
+  SDValue synthesize(MaskView &MV, VECustomDAG &CDAG, SDValue PartialV) override {
     SDValue ScalarSrcV;
     if (SourceElem.isElemInsert()) {
       ScalarSrcV = SourceElem.V;
@@ -996,7 +996,7 @@ struct ConstantElemOp final : public AbstractShuffleOp {
   ConstantElemOp(Constant *VecConstant) : VecConstant(VecConstant) {}
   ~ConstantElemOp() {}
 
-  SDValue synthesize(MaskView &MV, CustomDAG &CDAG, SDValue PartialV) override {
+  SDValue synthesize(MaskView &MV, VECustomDAG &CDAG, SDValue PartialV) override {
     EVT LegalResVT = PartialV.getValueType();
     const EVT PtrVT = MVT::i64;
     // const unsigned LegalNumElems = LegalResVT.getVectorNumElements();
@@ -1113,7 +1113,7 @@ struct GatherShuffleOp final : public AbstractShuffleOp {
 
   ~GatherShuffleOp() {}
 
-  SDValue synthesize(MaskView &MV, CustomDAG &CDAG, SDValue PartialV) override {
+  SDValue synthesize(MaskView &MV, VECustomDAG &CDAG, SDValue PartialV) override {
     // Spill the requires elements of \p SrcVectorV to the stack
     EVT LegalizedSrcVT =
         CDAG.legalizeVectorType(SrcVectorV, VVPExpansionMode::ToNextWidth);
@@ -1326,7 +1326,7 @@ raw_ostream &ShuffleAnalysis::print(raw_ostream &out) const {
   return out;
 }
 
-SDValue ShuffleAnalysis::synthesize(CustomDAG &CDAG, EVT LegalResultVT) {
+SDValue ShuffleAnalysis::synthesize(VECustomDAG &CDAG, EVT LegalResultVT) {
   LLVM_DEBUG(dbgs() << "Synthesized shuffle sequence:\n"; print(dbgs()));
 
   SDValue AccuV = CDAG.getUndef(LegalResultVT);

llvm/lib/Target/VE/ShuffleSynthesis.h

@@ -13,7 +13,7 @@
 #ifndef LLVM_LIB_TARGET_VE_SHUFFLESYNTHESIS_H
 #define LLVM_LIB_TARGET_VE_SHUFFLESYNTHESIS_H
 
-#include "CustomDAG.h"
+#include "VECustomDAG.h"
 #include "MaskView.h"
 #include "VE.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
@@ -116,17 +116,17 @@ struct MaskShuffleAnalysis {
 
   // match a 64 bit segment, mapping out all source bits
   // FIXME this implies knowledge about the underlying object structure
-  MaskShuffleAnalysis(MaskView& MV, CustomDAG &CDAG);
+  MaskShuffleAnalysis(MaskView& MV, VECustomDAG &CDAG);
 
   // Synthesize \p BitSelect, merging the result into \p Passthru
   SDValue synthesize(SDValue Passthru, BitSelect &BSel, SDValue SXV,
-                     CustomDAG &CDAG) const;
+                     VECustomDAG &CDAG) const;
 
   // Check whether the constant background of the result consists only of `1` bits (or undef)
   bool analyzeVectorSources(bool & AllTrue) const;
 
   // materialize the code to synthesize this operation
-  SDValue synthesize(CustomDAG &CDAG, EVT LegalMaskVT);
+  SDValue synthesize(VECustomDAG &CDAG, EVT LegalMaskVT);
 };
 
 enum IterControl {
@@ -184,7 +184,7 @@ struct PartialShuffleState {
 struct AbstractShuffleOp {
   virtual ~AbstractShuffleOp() {}
 
-  virtual SDValue synthesize(MaskView &MV, CustomDAG &CDAG,
+  virtual SDValue synthesize(MaskView &MV, VECustomDAG &CDAG,
                              SDValue PartialV) = 0;
   virtual void print(raw_ostream &out) const = 0;
 };
@@ -247,7 +247,7 @@ class ShuffleAnalysis {
   raw_ostream &print(raw_ostream &out) const;
 
   /// Synthesize the code planned in the analyze stage
-  SDValue synthesize(CustomDAG &CDAG, EVT LegalResultVT);
+  SDValue synthesize(VECustomDAG &CDAG, EVT LegalResultVT);
 };
 
 } // namespace llvm