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[AArch64][SVE] NFC: Add test file for predicate vector reductions.
This adds some tests for vector reductions which can and should be implemented with ptest as opposed to promoted ANDV/ORV reduction.
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‎llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
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define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) vscale_range(2, 0) {
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; CHECK-LABEL: ptest_v16i1_256bit_min_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #8
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: fcmeq p0.s, p0/z, z1.s, #0.0
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z2.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: eor z1.d, z2.d, z1.d
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: mov v1.d[1], v0.d[0]
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; CHECK-NEXT: orv b0, p0, z1.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
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ret i1 %v3
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}
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define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
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; CHECK-LABEL: ptest_v16i1_512bit_min_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
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ret i1 %v3
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}
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define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) {
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; CHECK-LABEL: ptest_v16i1_512bit_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
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ret i1 %v3
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}
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define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
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; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: fcmeq p0.s, p0/z, z1.s, #0.0
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z2.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: eor z1.d, z2.d, z1.d
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = bitcast float* %b to <16 x float>*
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%v4 = load <16 x float>, <16 x float>* %v3, align 4
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%v5 = fcmp une <16 x float> %v4, zeroinitializer
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%v6 = or <16 x i1> %v2, %v5
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%v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6)
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ret i1 %v7
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}
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declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)
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;
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; AND reduction.
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;
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define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) {
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; CHECK-LABEL: ptest_and_v16i1_512bit_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: fcmeq p0.s, p0/z, z1.s, #0.0
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: bic z0.d, z0.d, z1.d
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: andv b0, p0, z0.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = bitcast float* %b to <16 x float>*
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%v4 = load <16 x float>, <16 x float>* %v3, align 4
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%v5 = fcmp une <16 x float> %v4, zeroinitializer
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%v6 = and <16 x i1> %v2, %v5
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%v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)
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ret i1 %v7
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}
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define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
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; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0
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; CHECK-NEXT: fcmeq p0.s, p0/z, z1.s, #0.0
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: bic z0.d, z0.d, z1.d
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: andv b0, p0, z0.b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%v0 = bitcast float* %a to <16 x float>*
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%v1 = load <16 x float>, <16 x float>* %v0, align 4
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%v2 = fcmp une <16 x float> %v1, zeroinitializer
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%v3 = bitcast float* %b to <16 x float>*
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%v4 = load <16 x float>, <16 x float>* %v3, align 4
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%v5 = fcmp une <16 x float> %v4, zeroinitializer
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%v6 = and <16 x i1> %v2, %v5
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%v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)
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ret i1 %v7
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}
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declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)

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