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[RISCV] Prune more unnecessary vector pseudo instructions. NFC
For floating point specific vector instructions, we don't need pseudos for mf8. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D116460
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2 files changed

+83
-71
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 39 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1440,10 +1440,10 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
14401440
case CASE_VFMA_SPLATS(FNMSUB):
14411441
case CASE_VFMA_SPLATS(FNMACC):
14421442
case CASE_VFMA_SPLATS(FNMSAC):
1443-
case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1444-
case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1445-
case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1446-
case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV):
1443+
case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
1444+
case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
1445+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
1446+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
14471447
case CASE_VFMA_OPCODE_LMULS(MADD, VX):
14481448
case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
14491449
case CASE_VFMA_OPCODE_LMULS(MACC, VX):
@@ -1464,10 +1464,10 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
14641464
return false;
14651465
return true;
14661466
}
1467-
case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1468-
case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1469-
case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1470-
case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV):
1467+
case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
1468+
case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV):
1469+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV):
1470+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV):
14711471
case CASE_VFMA_OPCODE_LMULS(MADD, VV):
14721472
case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
14731473
// If the tail policy is undisturbed we can't commute.
@@ -1585,10 +1585,10 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
15851585
case CASE_VFMA_SPLATS(FNMADD):
15861586
case CASE_VFMA_SPLATS(FNMSAC):
15871587
case CASE_VFMA_SPLATS(FNMSUB):
1588-
case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1589-
case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1590-
case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1591-
case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV):
1588+
case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
1589+
case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
1590+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
1591+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
15921592
case CASE_VFMA_OPCODE_LMULS(MADD, VX):
15931593
case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
15941594
case CASE_VFMA_OPCODE_LMULS(MACC, VX):
@@ -1611,10 +1611,10 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
16111611
CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
16121612
CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
16131613
CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
1614-
CASE_VFMA_CHANGE_OPCODE_LMULS(FMACC, FMADD, VV)
1615-
CASE_VFMA_CHANGE_OPCODE_LMULS(FMSAC, FMSUB, VV)
1616-
CASE_VFMA_CHANGE_OPCODE_LMULS(FNMACC, FNMADD, VV)
1617-
CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSAC, FNMSUB, VV)
1614+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMACC, FMADD, VV)
1615+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMSAC, FMSUB, VV)
1616+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMACC, FNMADD, VV)
1617+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSAC, FNMSUB, VV)
16181618
CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX)
16191619
CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX)
16201620
CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VX)
@@ -1628,10 +1628,10 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
16281628
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
16291629
OpIdx1, OpIdx2);
16301630
}
1631-
case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1632-
case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1633-
case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1634-
case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV):
1631+
case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
1632+
case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV):
1633+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV):
1634+
case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV):
16351635
case CASE_VFMA_OPCODE_LMULS(MADD, VV):
16361636
case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
16371637
assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
@@ -1642,10 +1642,10 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
16421642
switch (MI.getOpcode()) {
16431643
default:
16441644
llvm_unreachable("Unexpected opcode");
1645-
CASE_VFMA_CHANGE_OPCODE_LMULS(FMADD, FMACC, VV)
1646-
CASE_VFMA_CHANGE_OPCODE_LMULS(FMSUB, FMSAC, VV)
1647-
CASE_VFMA_CHANGE_OPCODE_LMULS(FNMADD, FNMACC, VV)
1648-
CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSUB, FNMSAC, VV)
1645+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMADD, FMACC, VV)
1646+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMSUB, FMSAC, VV)
1647+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMADD, FNMACC, VV)
1648+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSUB, FNMSAC, VV)
16491649
CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV)
16501650
CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VV)
16511651
}
@@ -1674,36 +1674,42 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
16741674
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \
16751675
RISCV::PseudoV##OP##_##LMUL##_TIED
16761676

1677-
#define CASE_WIDEOP_OPCODE_LMULS(OP) \
1678-
CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
1679-
case CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
1677+
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP) \
1678+
CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
16801679
case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \
16811680
case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \
16821681
case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \
16831682
case CASE_WIDEOP_OPCODE_COMMON(OP, M4)
1683+
1684+
#define CASE_WIDEOP_OPCODE_LMULS(OP) \
1685+
CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
1686+
case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
16841687
// clang-format on
16851688

16861689
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \
16871690
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
16881691
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
16891692
break;
16901693

1691-
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
1692-
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
1694+
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \
16931695
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
16941696
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
16951697
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
16961698
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
16971699
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
16981700

1701+
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
1702+
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
1703+
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
1704+
16991705
MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
17001706
LiveVariables *LV,
17011707
LiveIntervals *LIS) const {
17021708
switch (MI.getOpcode()) {
17031709
default:
17041710
break;
1705-
case CASE_WIDEOP_OPCODE_LMULS(FWADD_WV):
1706-
case CASE_WIDEOP_OPCODE_LMULS(FWSUB_WV):
1711+
case CASE_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV):
1712+
case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV):
17071713
case CASE_WIDEOP_OPCODE_LMULS(WADD_WV):
17081714
case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV):
17091715
case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV):
@@ -1713,8 +1719,8 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
17131719
switch (MI.getOpcode()) {
17141720
default:
17151721
llvm_unreachable("Unexpected opcode");
1716-
CASE_WIDEOP_CHANGE_OPCODE_LMULS(FWADD_WV)
1717-
CASE_WIDEOP_CHANGE_OPCODE_LMULS(FWSUB_WV)
1722+
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWADD_WV)
1723+
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWSUB_WV)
17181724
CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADD_WV)
17191725
CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV)
17201726
CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV)

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