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Merge pull request #164 from sx-aurora-dev/feature/add-lcr-intrinsic-tests
[VE] Support communication register intrinsics
2 parents e0c5640 + 696a7bb commit ad523ac

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‎llvm/test/CodeGen/VE/VELIntrinsics/c/Makefile

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@@ -22,12 +22,13 @@ MERGER_TARGETS = vmrg.ll vshf.ll vcp.ll vex.ll
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MASK_TARGETS = vfmk.ll andm.ll orm.ll xorm.ll eqvm.ll nndm.ll negm.ll pcvm.ll \
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lzvm.ll tovm.ll
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REDUCTION_TARGETS = vsum.ll vfsum.ll vrmax.ll vrmin.ll vrand.ll vror.ll vrxor.ll
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CR_TARGETS = lcr.ll
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TRANSFER_TARGETS = svob.ll
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OTHERS_TARGETS = pack.ll extract.ll insert.ll
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TARGETS = $(LDSTMV_TARGETS) $(ARITH_TARGETS) $(LOGICAL_TARGETS) \
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$(SHIFT_TARGETS) $(FP_ARITH_TARGETS) $(MERGER_TARGETS) $(MASK_TARGETS) \
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$(REDUCTION_TARGETS) $(TRANSFER_TARGETS) $(OTHERS_TARGETS)
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$(REDUCTION_TARGETS) $(CR_TARGETS) $(TRANSFER_TARGETS) $(OTHERS_TARGETS)
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all: $(TARGETS)
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‎llvm/test/CodeGen/VE/VELIntrinsics/c/lcr.c

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#include "types.h"
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#include "velintrin.h"
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/// Test intrinsics for communication register
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///
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/// Note:
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/// We test LCR, SCR, TSCR, and FIDCR instructions.
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u64 lcr_sss(u64 sy, u64 sz) {
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return _vel_lcr_sss(sy, sz);
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}
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void scr_sss(u64 sx, u64 sy, u64 sz) {
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_vel_scr_sss(sx, sy, sz);
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}
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u64 tscr_ssss(u64 sx, u64 sy, u64 sz) {
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return _vel_tscr_ssss(sx, sy, sz);
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}
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#define VL_FIDCR(N) \
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u64 fidcr_ss ## N(u64 sy) { \
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return _vel_fidcr_sss(sy, N); \
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}
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VL_FIDCR(0)
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VL_FIDCR(1)
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VL_FIDCR(2)
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VL_FIDCR(3)
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VL_FIDCR(4)
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VL_FIDCR(5)
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VL_FIDCR(6)
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VL_FIDCR(7)
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// VL_FIDCR(8)

‎llvm/test/CodeGen/VE/VELIntrinsics/lcr.ll

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; RUN: llc < %s -mtriple=ve -mattr=+vpu,+packed | FileCheck %s
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;;; Test intrinsics for communication register
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;;;
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;;; Note:
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;;; We test LCR, SCR, TSCR, and FIDCR instructions.
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; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn
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define i64 @lcr_sss(i64 noundef %0, i64 noundef %1) {
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; CHECK-LABEL: lcr_sss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call i64 @llvm.ve.vl.lcr.sss(i64 %0, i64 %1)
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ret i64 %3
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}
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; Function Attrs: nofree nosync nounwind readnone
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declare i64 @llvm.ve.vl.lcr.sss(i64, i64)
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; Function Attrs: nounwind
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define void @scr_sss(i64 noundef %0, i64 noundef %1, i64 noundef %2) {
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; CHECK-LABEL: scr_sss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: scr %s0, %s1, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.scr.sss(i64 %0, i64 %1, i64 %2)
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.ve.vl.scr.sss(i64, i64, i64)
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; Function Attrs: nounwind
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define i64 @tscr_ssss(i64 noundef %0, i64 noundef %1, i64 noundef %2) {
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; CHECK-LABEL: tscr_ssss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tscr %s0, %s1, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call i64 @llvm.ve.vl.tscr.ssss(i64 %0, i64 %1, i64 %2)
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ret i64 %4
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}
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; Function Attrs: nounwind
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declare i64 @llvm.ve.vl.tscr.ssss(i64, i64, i64)
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; Function Attrs: nounwind
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define i64 @fidcr_ss0(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 0)
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ret i64 %2
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}
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; Function Attrs: nounwind
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declare i64 @llvm.ve.vl.fidcr.sss(i64, i32)
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; Function Attrs: nounwind
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define i64 @fidcr_ss1(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 1)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss2(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 2
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 2)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss3(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 3
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 3)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss4(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 4
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 4)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss5(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 5
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 5)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss6(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 6
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 6)
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ret i64 %2
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}
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; Function Attrs: nounwind
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define i64 @fidcr_ss7(i64 noundef %0) {
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; CHECK-LABEL: fidcr_ss7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fidcr %s0, %s0, 7
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 7)
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ret i64 %2
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}
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!2 = !{!"clang version 15.0.0 (git@kaz7.github.com:sx-aurora-dev/llvm-project.git e0c5640dba6e9ba1cd29ed8d59b85c6378e48ac7)"}

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