[RISCV] Set CostPerUse to 1 iff RVC is enabled

After D86836, we can define multiple cost values for
different cost models. So here we set CostPerUse to
1 iff RVC is enabled to avoid potential impact on RA.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117741

Author: pcwang-thead

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -347,3 +347,8 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
     Ops.push_back(dwarf::DW_OP_minus);
   }
 }
+
+unsigned
+RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
+  return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
+}

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

@@ -66,6 +66,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
 
   void getOffsetOpcodes(const StackOffset &Offset,
                         SmallVectorImpl<uint64_t> &Ops) const override;
+
+  unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
 };
 }
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -73,12 +73,11 @@ def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 // are not part of GPRC, the most restrictive register class used by the
 // compressed instruction set. This will influence the greedy register
 // allocator to reduce the use of registers that can't be encoded in 16 bit
-// instructions. This affects register allocation even when compressed
-// instruction isn't targeted, we see no major negative codegen impact.
+// instructions.
 
 let RegAltNameIndices = [ABIRegAltName] in {
   def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
-  let CostPerUse = [1] in {
+  let CostPerUse = [0, 1] in {
   def X1  : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
   def X2  : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
   def X3  : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
@@ -95,7 +94,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
   def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
   def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
   def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
-  let CostPerUse = [1] in {
+  let CostPerUse = [0, 1] in {
   def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
   def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
   def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;

llvm/test/CodeGen/RISCV/add-before-shl.ll

@@ -163,23 +163,23 @@ define i128 @add_wide_operand(i128 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a2, 0(a1)
 ; RV32I-NEXT:    lw a3, 4(a1)
-; RV32I-NEXT:    lw a6, 12(a1)
+; RV32I-NEXT:    lw a4, 12(a1)
 ; RV32I-NEXT:    lw a1, 8(a1)
 ; RV32I-NEXT:    srli a5, a2, 29
-; RV32I-NEXT:    slli a4, a3, 3
-; RV32I-NEXT:    or a4, a4, a5
+; RV32I-NEXT:    slli a6, a3, 3
+; RV32I-NEXT:    or a5, a6, a5
 ; RV32I-NEXT:    srli a3, a3, 29
-; RV32I-NEXT:    slli a5, a1, 3
-; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    slli a6, a1, 3
+; RV32I-NEXT:    or a3, a6, a3
 ; RV32I-NEXT:    srli a1, a1, 29
-; RV32I-NEXT:    slli a5, a6, 3
-; RV32I-NEXT:    or a1, a5, a1
+; RV32I-NEXT:    slli a4, a4, 3
+; RV32I-NEXT:    or a1, a4, a1
 ; RV32I-NEXT:    slli a2, a2, 3
-; RV32I-NEXT:    lui a5, 128
-; RV32I-NEXT:    add a1, a1, a5
+; RV32I-NEXT:    lui a4, 128
+; RV32I-NEXT:    add a1, a1, a4
 ; RV32I-NEXT:    sw a2, 0(a0)
 ; RV32I-NEXT:    sw a3, 8(a0)
-; RV32I-NEXT:    sw a4, 4(a0)
+; RV32I-NEXT:    sw a5, 4(a0)
 ; RV32I-NEXT:    sw a1, 12(a0)
 ; RV32I-NEXT:    jalr zero, 0(ra)
 ;

llvm/test/CodeGen/RISCV/addcarry.ll

@@ -10,19 +10,19 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
 ; RISCV32-LABEL: addcarry:
 ; RISCV32:       # %bb.0:
 ; RISCV32-NEXT:    mul a4, a0, a3
-; RISCV32-NEXT:    mulhu a7, a0, a2
-; RISCV32-NEXT:    add a4, a7, a4
-; RISCV32-NEXT:    mul a5, a1, a2
-; RISCV32-NEXT:    add a6, a4, a5
-; RISCV32-NEXT:    sltu t0, a6, a4
-; RISCV32-NEXT:    sltu a4, a4, a7
-; RISCV32-NEXT:    mulhu a5, a0, a3
-; RISCV32-NEXT:    add a4, a5, a4
-; RISCV32-NEXT:    mulhu a5, a1, a2
-; RISCV32-NEXT:    add a4, a4, a5
-; RISCV32-NEXT:    add a4, a4, t0
-; RISCV32-NEXT:    mul a5, a1, a3
-; RISCV32-NEXT:    add a5, a4, a5
+; RISCV32-NEXT:    mulhu a5, a0, a2
+; RISCV32-NEXT:    add a6, a5, a4
+; RISCV32-NEXT:    mul a4, a1, a2
+; RISCV32-NEXT:    add a4, a6, a4
+; RISCV32-NEXT:    sltu a7, a4, a6
+; RISCV32-NEXT:    sltu a5, a6, a5
+; RISCV32-NEXT:    mulhu a6, a0, a3
+; RISCV32-NEXT:    add a5, a6, a5
+; RISCV32-NEXT:    mulhu a6, a1, a2
+; RISCV32-NEXT:    add a5, a5, a6
+; RISCV32-NEXT:    add a5, a5, a7
+; RISCV32-NEXT:    mul a6, a1, a3
+; RISCV32-NEXT:    add a5, a5, a6
 ; RISCV32-NEXT:    bgez a1, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1:
 ; RISCV32-NEXT:    sub a5, a5, a2
@@ -32,9 +32,9 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
 ; RISCV32-NEXT:    sub a5, a5, a0
 ; RISCV32-NEXT:  .LBB0_4:
 ; RISCV32-NEXT:    slli a1, a5, 30
-; RISCV32-NEXT:    srli a3, a6, 2
+; RISCV32-NEXT:    srli a3, a4, 2
 ; RISCV32-NEXT:    or a1, a1, a3
-; RISCV32-NEXT:    slli a3, a6, 30
+; RISCV32-NEXT:    slli a3, a4, 30
 ; RISCV32-NEXT:    mul a0, a0, a2
 ; RISCV32-NEXT:    srli a0, a0, 2
 ; RISCV32-NEXT:    or a0, a3, a0