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Simon Moll
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[VE] packed strided VST splitting test
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‎llvm/test/CodeGen/VE/Packed/vp_strided_store.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu,+packed | FileCheck %s
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declare void @llvm.experimental.vp.strided.store.v512f32.i64(<512 x float> %val, float* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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define fastcc void @vp_strided_store_v512f32_rrm(<512 x float> %val, float* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f32_rrm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s3, 1, %s2
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; CHECK-NEXT: and %s3, %s3, (32)0
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; CHECK-NEXT: srl %s3, %s3, 1
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; CHECK-NEXT: sll %s4, %s1, 1
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vstu %v0, %s4, %s0, %vm2
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: and %s1, %s2, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vshf %v0, %v0, %v0, 4
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vstu %v0, %s4, %s0, %vm3
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; CHECK-NEXT: b.l.t (, %s10)
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call void @llvm.experimental.vp.strided.store.v512f32.i64(<512 x float> %val, float* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512f32_rr(<512 x float> %val, float* %ptr, i64 %stride, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f32_rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s3, 1, %s2
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; CHECK-NEXT: and %s3, %s3, (32)0
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; CHECK-NEXT: srl %s3, %s3, 1
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; CHECK-NEXT: sll %s4, %s1, 1
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vstu %v0, %s4, %s0
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: and %s1, %s2, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vshf %v0, %v0, %v0, 4
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vstu %v0, %s4, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512f32.i64(<512 x float> %val, float* %ptr, i64 %stride, <512 x i1> %allones, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512f32_ri(<512 x float> %val, float* %ptr, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f32_ri:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s2, 1, %s1
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vstu %v0, 48, %s0
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vshf %v0, %v0, %v0, 4
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; CHECK-NEXT: lea %s0, 24(, %s0)
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vstu %v0, 48, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512f32.i64(<512 x float> %val, float* %ptr, i64 24, <512 x i1> %allones, i32 %evl)
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ret void
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}
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declare void @llvm.experimental.vp.strided.store.v512i32.i64(<512 x i32> %val, i32* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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define fastcc void @vp_strided_store_v512i32_rrm(<512 x i32> %val, i32* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i32_rrm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.l %s3, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s1, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vstl %v0, %s1, %s3, %vm3
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; CHECK-NEXT: vshf %v0, %v0, %v0, 0
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; CHECK-NEXT: vstl %v0, %s1, %s0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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call void @llvm.experimental.vp.strided.store.v512i32.i64(<512 x i32> %val, i32* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512i32_rr(<512 x i32> %val, i32* %ptr, i64 %stride, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i32_rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.l %s3, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s1, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vstl %v0, %s1, %s3
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; CHECK-NEXT: vshf %v0, %v0, %v0, 0
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; CHECK-NEXT: vstl %v0, %s1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512i32.i64(<512 x i32> %val, i32* %ptr, i64 %stride, <512 x i1> %allones, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512i32_ri(<512 x i32> %val, i32* %ptr, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i32_ri:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lea %s2, 24(, %s0)
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vstl %v0, 48, %s2
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; CHECK-NEXT: vshf %v0, %v0, %v0, 0
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; CHECK-NEXT: vstl %v0, 48, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512i32.i64(<512 x i32> %val, i32* %ptr, i64 24, <512 x i1> %allones, i32 %evl)
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ret void
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}
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declare void @llvm.experimental.vp.strided.store.v512f64.i64(<512 x double> %val, double* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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define fastcc void @vp_strided_store_v512f64_rrm(<512 x double> %val, double* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f64_rrm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s3, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, %s3, %s0, %vm2
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: vst %v1, %s3, %s0, %vm3
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; CHECK-NEXT: b.l.t (, %s10)
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call void @llvm.experimental.vp.strided.store.v512f64.i64(<512 x double> %val, double* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512f64_rr(<512 x double> %val, double* %ptr, i64 %stride, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f64_rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s3, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, %s3, %s0
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: vst %v1, %s3, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512f64.i64(<512 x double> %val, double* %ptr, i64 %stride, <512 x i1> %allones, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512f64_ri(<512 x double> %val, double* %ptr, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512f64_ri:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vst %v0, 48, %s0
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; CHECK-NEXT: lea %s0, 24(, %s0)
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; CHECK-NEXT: vst %v1, 48, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512f64.i64(<512 x double> %val, double* %ptr, i64 24, <512 x i1> %allones, i32 %evl)
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ret void
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}
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declare void @llvm.experimental.vp.strided.store.v512i64.i64(<512 x i64> %val, i64* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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define fastcc void @vp_strided_store_v512i64_rrm(<512 x i64> %val, i64* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i64_rrm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s3, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, %s3, %s0, %vm2
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: vst %v1, %s3, %s0, %vm3
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; CHECK-NEXT: b.l.t (, %s10)
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call void @llvm.experimental.vp.strided.store.v512i64.i64(<512 x i64> %val, i64* %ptr, i64 %stride, <512 x i1> %mask, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512i64_rr(<512 x i64> %val, i64* %ptr, i64 %stride, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i64_rr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s2, 1, %s2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: sll %s3, %s1, 1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, %s3, %s0
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; CHECK-NEXT: adds.l %s0, %s0, %s1
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; CHECK-NEXT: vst %v1, %s3, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512i64.i64(<512 x i64> %val, i64* %ptr, i64 %stride, <512 x i1> %allones, i32 %evl)
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ret void
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}
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define fastcc void @vp_strided_store_v512i64_ri(<512 x i64> %val, i64* %ptr, i32 %evl) {
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; CHECK-LABEL: vp_strided_store_v512i64_ri:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vst %v0, 48, %s0
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; CHECK-NEXT: lea %s0, 24(, %s0)
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; CHECK-NEXT: vst %v1, 48, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%one = insertelement <512 x i1> undef, i1 1, i32 0
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%allones = shufflevector <512 x i1> %one, <512 x i1> undef, <512 x i32> zeroinitializer
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call void @llvm.experimental.vp.strided.store.v512i64.i64(<512 x i64> %val, i64* %ptr, i64 24, <512 x i1> %allones, i32 %evl)
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ret void
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}

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