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[RISCV][RFC] add inst support of zbkb
This commit add instructions supports of `zbkb` which defined in scalar cryptography extension version v1.0.0 (has been ratified already). Most of the zbkb directives reuse parts of the zbp and zbb directives, so this patch just modified some of the inst aliases and predicates. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117640
1 parent 82af950 commit 7ee1c16

18 files changed

+170
-41
lines changed

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
5555
{"zbb", RISCVExtensionVersion{1, 0}},
5656
{"zbc", RISCVExtensionVersion{1, 0}},
5757
{"zbs", RISCVExtensionVersion{1, 0}},
58+
59+
{"zbkb", RISCVExtensionVersion{1, 0}},
5860
};
5961

6062
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,26 @@ def HasStdExtZbbOrZbp
143143
"'Zbb' (Base 'B' Instructions) or "
144144
"'Zbp' (Permutation 'B' Instructions)">;
145145

146+
def FeatureStdExtZbkb
147+
: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
148+
"'Zbkb' (Bitmanip instructions for Cryptography)">;
149+
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
150+
AssemblerPredicate<(all_of FeatureStdExtZbkb),
151+
"'Zbkb' (Bitmanip instructions for Cryptography)">;
152+
153+
def HasStdExtZbpOrZbkb
154+
: Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
155+
AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
156+
"'Zbp' (Permutation 'B' Instructions) or "
157+
"'Zbkb' (Bitmanip instructions for Cryptography)">;
158+
159+
def HasStdExtZbbOrZbpOrZbkb
160+
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
161+
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb),
162+
"'Zbb' (Base 'B' Instructions) or "
163+
"'Zbp' (Permutation 'B' Instructions) or "
164+
"'Zbkb' (Bitmanip instructions for Cryptography)">;
165+
146166
def FeatureNoRVCHints
147167
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
148168
"Disable RVC Hint Instructions.">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Lines changed: 29 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -313,14 +313,14 @@ class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
313313
// Instructions
314314
//===----------------------------------------------------------------------===//
315315

316-
let Predicates = [HasStdExtZbbOrZbp] in {
316+
let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
317317
def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
318318
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
319319
def ORN : ALU_rr<0b0100000, 0b110, "orn">,
320320
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
321321
def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
322322
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
323-
} // Predicates = [HasStdExtZbbOrZbp]
323+
} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
324324

325325
let Predicates = [HasStdExtZba] in {
326326
def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
@@ -331,12 +331,12 @@ def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
331331
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
332332
} // Predicates = [HasStdExtZba]
333333

334-
let Predicates = [HasStdExtZbbOrZbp] in {
334+
let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
335335
def ROL : ALU_rr<0b0110000, 0b001, "rol">,
336336
Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
337337
def ROR : ALU_rr<0b0110000, 0b101, "ror">,
338338
Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
339-
} // Predicates = [HasStdExtZbbOrZbp]
339+
} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
340340

341341
let Predicates = [HasStdExtZbs] in {
342342
def BCLR : ALU_rr<0b0100100, 0b001, "bclr">,
@@ -360,7 +360,7 @@ def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
360360
def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
361361
} // Predicates = [HasStdExtZbp]
362362

363-
let Predicates = [HasStdExtZbbOrZbp] in
363+
let Predicates = [HasStdExtZbbOrZbpOrZbkb] in
364364
def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
365365
Sched<[WriteRotateImm, ReadRotateImm]>;
366366

@@ -471,11 +471,13 @@ def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
471471
def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
472472
} // Predicates = [HasStdExtZbe]
473473

474-
let Predicates = [HasStdExtZbp] in {
474+
let Predicates = [HasStdExtZbpOrZbkb] in {
475475
def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
476-
def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
477476
def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
478-
} // Predicates = [HasStdExtZbp]
477+
} // Predicates = [HasStdExtZbpOrZbkb]
478+
479+
let Predicates = [HasStdExtZbp] in
480+
def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
479481

480482
let Predicates = [HasStdExtZbm, IsRV64] in {
481483
def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
@@ -504,7 +506,7 @@ def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
504506
Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
505507
} // Predicates = [HasStdExtZbb, IsRV64]
506508

507-
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
509+
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
508510
def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
509511
Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
510512
def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
@@ -520,7 +522,7 @@ let Predicates = [HasStdExtZbp, IsRV64] in {
520522
def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
521523
} // Predicates = [HasStdExtZbp, IsRV64]
522524

523-
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
525+
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in
524526
def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
525527
Sched<[WriteRotateImm32, ReadRotateImm32]>;
526528

@@ -559,10 +561,11 @@ def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
559561
def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
560562
} // Predicates = [HasStdExtZbe, IsRV64]
561563

562-
let Predicates = [HasStdExtZbp, IsRV64] in {
564+
let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
563565
def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
566+
567+
let Predicates = [HasStdExtZbp, IsRV64] in
564568
def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
565-
} // Predicates = [HasStdExtZbp, IsRV64]
566569

567570
let Predicates = [HasStdExtZbf, IsRV64] in
568571
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
@@ -593,21 +596,21 @@ def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
593596
// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
594597
// or gorci. Since Zbb is closer to being finalized than Zbp this will be
595598
// misleading to users.
596-
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
599+
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32] in {
597600
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
598601
def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
599602
"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
600603
let imm12 = { 0b01101, 0b0011000 };
601604
}
602-
} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
605+
} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32]
603606

604-
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
607+
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
605608
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
606609
def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
607610
"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
608611
let imm12 = { 0b01101, 0b0111000 };
609612
}
610-
} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
613+
} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
611614

612615
let Predicates = [HasStdExtZbbOrZbp] in {
613616
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
@@ -617,6 +620,15 @@ def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
617620
}
618621
} // Predicates = [HasStdExtZbbOrZbp]
619622

623+
let Predicates = [HasStdExtZbpOrZbkb] in
624+
def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">;
625+
626+
let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
627+
def ZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">;
628+
def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">;
629+
} // Predicates = [HasStdExtZbkb, IsRV32]
630+
631+
620632
//===----------------------------------------------------------------------===//
621633
// Pseudo Instructions
622634
//===----------------------------------------------------------------------===//
@@ -631,11 +643,11 @@ def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
631643
def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
632644
def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
633645
def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
634-
def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
635646
def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
636647
def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
637648
def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
638649
def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
650+
def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>;
639651

640652
def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
641653
def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
@@ -675,8 +687,6 @@ def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
675687
def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
676688
def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
677689
def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
678-
def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
679-
def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
680690

681691
def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
682692
def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;

‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
1717
let LoadLatency = 3;
1818
let MispredictPenalty = 3;
1919
let CompleteModel = false;
20-
let UnsupportedFeatures = [HasVInstructions, HasVInstructionsI64];
20+
let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasVInstructionsI64];
2121
}
2222

2323
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
1515
let LoadLatency = 3;
1616
let MispredictPenalty = 3;
1717
let CompleteModel = 0;
18-
let UnsupportedFeatures = [HasVInstructions];
18+
let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions];
1919
}
2020

2121
// The SiFive7 microarchitecture has two pipelines: A and B.

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
8383
bool HasStdExtZve64d = false;
8484
bool HasStdExtZfhmin = false;
8585
bool HasStdExtZfh = false;
86+
bool HasStdExtZbkb = false;
8687
bool HasRV64 = false;
8788
bool IsRV32E = false;
8889
bool EnableLinkerRelax = false;
@@ -156,6 +157,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
156157
bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
157158
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
158159
bool hasStdExtZfh() const { return HasStdExtZfh; }
160+
bool hasStdExtZbkb() const { return HasStdExtZbkb; }
159161
bool is64Bit() const { return HasRV64; }
160162
bool isRV32E() const { return IsRV32E; }
161163
bool enableLinkerRelax() const { return EnableLinkerRelax; }

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
2020
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
2121
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
22+
; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
2223
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
2324
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
2425
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -38,6 +39,7 @@
3839
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
3940
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
4041
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
42+
; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
4143

4244

4345
; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -59,6 +61,7 @@
5961
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
6062
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
6163
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
64+
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
6265

6366
; RV64M: .attribute 5, "rv64i2p0_m2p0"
6467
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -79,6 +82,7 @@
7982
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
8083
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
8184
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
85+
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
8286

8387
define i32 @addi(i32 %a) {
8488
%1 = add i32 %a, 1

‎llvm/test/CodeGen/RISCV/rv32zbp.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1491,7 +1491,7 @@ define i32 @grev7_i32(i32 %a) nounwind {
14911491
;
14921492
; RV32ZBP-LABEL: grev7_i32:
14931493
; RV32ZBP: # %bb.0:
1494-
; RV32ZBP-NEXT: rev.b a0, a0
1494+
; RV32ZBP-NEXT: grevi a0, a0, 7
14951495
; RV32ZBP-NEXT: ret
14961496
%and1 = shl i32 %a, 1
14971497
%shl1 = and i32 %and1, -1431655766
@@ -1560,8 +1560,8 @@ define i64 @grev7_i64(i64 %a) nounwind {
15601560
;
15611561
; RV32ZBP-LABEL: grev7_i64:
15621562
; RV32ZBP: # %bb.0:
1563-
; RV32ZBP-NEXT: rev.b a0, a0
1564-
; RV32ZBP-NEXT: rev.b a1, a1
1563+
; RV32ZBP-NEXT: grevi a0, a0, 7
1564+
; RV32ZBP-NEXT: grevi a1, a1, 7
15651565
; RV32ZBP-NEXT: ret
15661566
%and1 = shl i64 %a, 1
15671567
%shl1 = and i64 %and1, -6148914691236517206
@@ -2175,7 +2175,7 @@ define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
21752175
;
21762176
; RV32ZBP-LABEL: bitreverse_i8:
21772177
; RV32ZBP: # %bb.0:
2178-
; RV32ZBP-NEXT: rev.b a0, a0
2178+
; RV32ZBP-NEXT: grevi a0, a0, 7
21792179
; RV32ZBP-NEXT: ret
21802180
%1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
21812181
ret i8 %1
@@ -2450,7 +2450,7 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
24502450
;
24512451
; RV32ZBP-LABEL: bitreverse_bswap_i32:
24522452
; RV32ZBP: # %bb.0:
2453-
; RV32ZBP-NEXT: rev.b a0, a0
2453+
; RV32ZBP-NEXT: grevi a0, a0, 7
24542454
; RV32ZBP-NEXT: ret
24552455
%1 = call i32 @llvm.bitreverse.i32(i32 %a)
24562456
%2 = call i32 @llvm.bswap.i32(i32 %1)
@@ -2539,8 +2539,8 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
25392539
;
25402540
; RV32ZBP-LABEL: bitreverse_bswap_i64:
25412541
; RV32ZBP: # %bb.0:
2542-
; RV32ZBP-NEXT: rev.b a0, a0
2543-
; RV32ZBP-NEXT: rev.b a1, a1
2542+
; RV32ZBP-NEXT: grevi a0, a0, 7
2543+
; RV32ZBP-NEXT: grevi a1, a1, 7
25442544
; RV32ZBP-NEXT: ret
25452545
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
25462546
%2 = call i64 @llvm.bswap.i64(i64 %1)

‎llvm/test/CodeGen/RISCV/rv64zbp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,7 +1438,7 @@ define i64 @grev7_i64(i64 %a) nounwind {
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;
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; RV64ZBP-LABEL: grev7_i64:
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; RV64ZBP: # %bb.0:
1441-
; RV64ZBP-NEXT: rev.b a0, a0
1441+
; RV64ZBP-NEXT: grevi a0, a0, 7
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; RV64ZBP-NEXT: ret
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%and1 = shl i64 %a, 1
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%shl1 = and i64 %and1, -6148914691236517206
@@ -2481,7 +2481,7 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
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;
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; RV64ZBP-LABEL: bitreverse_bswap_i64:
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; RV64ZBP: # %bb.0:
2484-
; RV64ZBP-NEXT: rev.b a0, a0
2484+
; RV64ZBP-NEXT: grevi a0, a0, 7
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; RV64ZBP-NEXT: ret
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%1 = call i64 @llvm.bitreverse.i64(i64 %a)
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%2 = call i64 @llvm.bswap.i64(i64 %1)

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,3 +127,6 @@
127127

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.attribute arch, "rv32ifd_zve64d0p10"
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# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
130+
131+
.attribute arch, "rv32i_zbkb1p0"
132+
# CHECK: attribute 5, "rv32i2p0_zbkb1p0"

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