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Simon Moll
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[VE] Packed v512i32 isel and tests
Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D118332
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‎llvm/lib/Target/VE/VVPInstrPatternsVec.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,24 @@ defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
237237
f64, v256f64, "VFDIVD",
238238
f32, v256f32, "VFDIVS">;
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240+
defm : Binary_rv_vv<c_vvp_and,
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i64, v512i32, v512i1, "PVAND">;
242+
defm : Binary_rv_vv<c_vvp_or,
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i64, v512i32, v512i1, "PVOR">;
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defm : Binary_rv_vv<c_vvp_xor,
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i64, v512i32, v512i1, "PVXOR">;
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defm : Binary_rv_vv<c_vvp_add,
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i64, v512i32, v512i1, "PVADDU">;
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defm : Binary_rv_vv<vvp_sub,
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i64, v512i32, v512i1, "PVSUBU">;
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defm : Binary_vr_vv<vvp_srl,
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i64, v512i32, v512i1, "PVSRL">;
253+
defm : Binary_vr_vv<vvp_sra,
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i64, v512i32, v512i1, "PVSRA">;
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defm : Binary_vr_vv<vvp_shl,
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i64, v512i32, v512i1, "PVSLL">;
257+
240258
defm : Binary_rv_vv<c_vvp_fadd,
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i64, v512f32, v512i1, "PVFADD">;
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defm : Binary_rv_vv<c_vvp_fmul,

‎llvm/test/CodeGen/VE/Packed/vp_add.ll

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
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declare <512 x i32> @llvm.vp.add.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
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define fastcc <512 x i32> @test_vp_add_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_add_v512i32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvaddu %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
17+
}
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define fastcc <512 x i32> @test_vp_add_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_add_v512i32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
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%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
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}
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define fastcc <512 x i32> @test_vp_add_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_add_v512i32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
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%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
55+
}

‎llvm/test/CodeGen/VE/Packed/vp_and.ll

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x i32> @llvm.vp.and.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
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define fastcc <512 x i32> @test_vp_and_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_and_v512i32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvand %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
17+
}
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define fastcc <512 x i32> @test_vp_and_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_and_v512i32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
33+
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
36+
}
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define fastcc <512 x i32> @test_vp_and_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
39+
; CHECK-LABEL: test_vp_and_v512i32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
51+
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
52+
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
53+
%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
54+
ret <512 x i32> %r0
55+
}

‎llvm/test/CodeGen/VE/Packed/vp_or.ll

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x i32> @llvm.vp.or.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
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define fastcc <512 x i32> @test_vp_or_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_or_v512i32_vv:
8+
; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvor %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x i32> %r0
17+
}
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define fastcc <512 x i32> @test_vp_or_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_or_v512i32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
29+
; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
32+
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
33+
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
34+
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
35+
ret <512 x i32> %r0
36+
}
37+
38+
define fastcc <512 x i32> @test_vp_or_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
39+
; CHECK-LABEL: test_vp_or_v512i32_vr:
40+
; CHECK: # %bb.0:
41+
; CHECK-NEXT: and %s0, %s0, (32)0
42+
; CHECK-NEXT: sll %s2, %s0, 32
43+
; CHECK-NEXT: and %s0, %s0, (32)0
44+
; CHECK-NEXT: or %s0, %s0, %s2
45+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
46+
; CHECK-NEXT: and %s1, %s1, (32)0
47+
; CHECK-NEXT: srl %s1, %s1, 1
48+
; CHECK-NEXT: lvl %s1
49+
; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
50+
; CHECK-NEXT: b.l.t (, %s10)
51+
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
52+
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
53+
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
54+
ret <512 x i32> %r0
55+
}

‎llvm/test/CodeGen/VE/Packed/vp_shl.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <512 x i32> @llvm.vp.shl.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
5+
6+
define fastcc <512 x i32> @test_vp_shl_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_shl_v512i32_vv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
13+
; CHECK-NEXT: pvsll %v0, %v0, %v1, %vm2
14+
; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x i32> %r0
17+
}
18+
19+
define fastcc <512 x i32> @test_vp_shl_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_shl_v512i32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s0, %s0, (32)0
23+
; CHECK-NEXT: sll %s2, %s0, 32
24+
; CHECK-NEXT: and %s0, %s0, (32)0
25+
; CHECK-NEXT: or %s0, %s0, %s2
26+
; CHECK-NEXT: lea %s2, 256
27+
; CHECK-NEXT: lvl %s2
28+
; CHECK-NEXT: vbrd %v1, %s0
29+
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
30+
; CHECK-NEXT: and %s0, %s0, (32)0
31+
; CHECK-NEXT: srl %s0, %s0, 1
32+
; CHECK-NEXT: lvl %s0
33+
; CHECK-NEXT: pvsll %v0, %v1, %v0, %vm2
34+
; CHECK-NEXT: b.l.t (, %s10)
35+
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
36+
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
37+
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
38+
ret <512 x i32> %r0
39+
}
40+
41+
define fastcc <512 x i32> @test_vp_shl_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
42+
; CHECK-LABEL: test_vp_shl_v512i32_vr:
43+
; CHECK: # %bb.0:
44+
; CHECK-NEXT: and %s0, %s0, (32)0
45+
; CHECK-NEXT: sll %s2, %s0, 32
46+
; CHECK-NEXT: and %s0, %s0, (32)0
47+
; CHECK-NEXT: or %s0, %s0, %s2
48+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
49+
; CHECK-NEXT: and %s1, %s1, (32)0
50+
; CHECK-NEXT: srl %s1, %s1, 1
51+
; CHECK-NEXT: lvl %s1
52+
; CHECK-NEXT: pvsll %v0, %v0, %s0, %vm2
53+
; CHECK-NEXT: b.l.t (, %s10)
54+
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
55+
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
56+
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
57+
ret <512 x i32> %r0
58+
}

‎llvm/test/CodeGen/VE/Packed/vp_sra.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
5+
6+
define fastcc <512 x i32> @test_vp_ashr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_ashr_v512i32_vv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
13+
; CHECK-NEXT: pvsra %v0, %v0, %v1, %vm2
14+
; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x i32> %r0
17+
}
18+
19+
define fastcc <512 x i32> @test_vp_ashr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_ashr_v512i32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s0, %s0, (32)0
23+
; CHECK-NEXT: sll %s2, %s0, 32
24+
; CHECK-NEXT: and %s0, %s0, (32)0
25+
; CHECK-NEXT: or %s0, %s0, %s2
26+
; CHECK-NEXT: lea %s2, 256
27+
; CHECK-NEXT: lvl %s2
28+
; CHECK-NEXT: vbrd %v1, %s0
29+
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
30+
; CHECK-NEXT: and %s0, %s0, (32)0
31+
; CHECK-NEXT: srl %s0, %s0, 1
32+
; CHECK-NEXT: lvl %s0
33+
; CHECK-NEXT: pvsra %v0, %v1, %v0, %vm2
34+
; CHECK-NEXT: b.l.t (, %s10)
35+
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
36+
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
37+
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
38+
ret <512 x i32> %r0
39+
}
40+
41+
define fastcc <512 x i32> @test_vp_ashr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
42+
; CHECK-LABEL: test_vp_ashr_v512i32_vr:
43+
; CHECK: # %bb.0:
44+
; CHECK-NEXT: and %s0, %s0, (32)0
45+
; CHECK-NEXT: sll %s2, %s0, 32
46+
; CHECK-NEXT: and %s0, %s0, (32)0
47+
; CHECK-NEXT: or %s0, %s0, %s2
48+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
49+
; CHECK-NEXT: and %s1, %s1, (32)0
50+
; CHECK-NEXT: srl %s1, %s1, 1
51+
; CHECK-NEXT: lvl %s1
52+
; CHECK-NEXT: pvsra %v0, %v0, %s0, %vm2
53+
; CHECK-NEXT: b.l.t (, %s10)
54+
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
55+
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
56+
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
57+
ret <512 x i32> %r0
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}

‎llvm/test/CodeGen/VE/Packed/vp_srl.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
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define fastcc <512 x i32> @test_vp_lshr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_lshr_v512i32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvsrl %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
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}
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define fastcc <512 x i32> @test_vp_lshr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_lshr_v512i32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vbrd %v1, %s0
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; CHECK-NEXT: adds.w.sx %s0, 1, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvsrl %v0, %v1, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
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%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
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}
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define fastcc <512 x i32> @test_vp_lshr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_lshr_v512i32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s2, %s0, 32
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvsrl %v0, %v0, %s0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
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%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
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ret <512 x i32> %r0
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}

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