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[RISCV] Disable EEW=64 for index values when XLEN=32.
Disable EEW=64 for vector index load/store when XLEN=32. Differential Revision: https://reviews.llvm.org/D106518
1 parent 6fab274 commit 6b8362e

18 files changed

+1579
-5649
lines changed

‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
216216
string HeaderCode = "";
217217

218218
// Sub extension of vector spec. Currently only support Zvlsseg.
219-
string RequiredExtension = "";
219+
list<string> RequiredExtensions = [];
220220

221221
// Number of fields for Zvlsseg.
222222
int NF = 1;
@@ -707,7 +707,7 @@ multiclass RVVIndexedLoad<string op> {
707707
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
708708
}] in {
709709
foreach type = TypeList in {
710-
foreach eew_list = EEWList in {
710+
foreach eew_list = EEWList[0-2] in {
711711
defvar eew = eew_list[0];
712712
defvar eew_type = eew_list[1];
713713
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
@@ -717,6 +717,15 @@ multiclass RVVIndexedLoad<string op> {
717717
}
718718
}
719719
}
720+
defvar eew64 = "64";
721+
defvar eew64_type = "(Log2EEW:6)";
722+
let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
723+
RequiredExtensions = ["RV64"] in {
724+
def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;
725+
if !not(IsFloat<type>.val) then {
726+
def: RVVBuiltin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
727+
}
728+
}
720729
}
721730
}
722731
}
@@ -797,7 +806,7 @@ multiclass RVVIndexedStore<string op> {
797806
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[4]->getType()};
798807
}] in {
799808
foreach type = TypeList in {
800-
foreach eew_list = EEWList in {
809+
foreach eew_list = EEWList[0-2] in {
801810
defvar eew = eew_list[0];
802811
defvar eew_type = eew_list[1];
803812
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
@@ -807,6 +816,15 @@ multiclass RVVIndexedStore<string op> {
807816
}
808817
}
809818
}
819+
defvar eew64 = "64";
820+
defvar eew64_type = "(Log2EEW:6)";
821+
let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
822+
RequiredExtensions = ["RV64"] in {
823+
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
824+
if !not(IsFloat<type>.val) then {
825+
def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
826+
}
827+
}
810828
}
811829
}
812830
}
@@ -1549,7 +1567,7 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
15491567
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
15501568

15511569
// 7.8 Vector Load/Store Segment Instructions
1552-
let RequiredExtension = "Zvlsseg" in {
1570+
let RequiredExtensions = ["Zvlsseg"] in {
15531571
defm : RVVUnitStridedSegLoad<"vlseg">;
15541572
defm : RVVUnitStridedSegLoadFF<"vlseg">;
15551573
defm : RVVStridedSegLoad<"vlsseg">;

‎clang/utils/TableGen/RISCVVEmitter.cpp

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ enum RISCVExtension : uint8_t {
141141
D = 1 << 2,
142142
Zfh = 1 << 3,
143143
Zvlsseg = 1 << 4,
144+
RV64 = 1 << 5,
144145
};
145146

146147
// TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -174,7 +175,7 @@ class RVVIntrinsic {
174175
bool HasNoMaskedOverloaded, bool HasAutoDef,
175176
StringRef ManualCodegen, const RVVTypes &Types,
176177
const std::vector<int64_t> &IntrinsicTypes,
177-
StringRef RequiredExtension, unsigned NF);
178+
const std::vector<StringRef> &RequiredExtensions, unsigned NF);
178179
~RVVIntrinsic() = default;
179180

180181
StringRef getBuiltinName() const { return BuiltinName; }
@@ -764,7 +765,8 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
764765
bool HasNoMaskedOverloaded, bool HasAutoDef,
765766
StringRef ManualCodegen, const RVVTypes &OutInTypes,
766767
const std::vector<int64_t> &NewIntrinsicTypes,
767-
StringRef RequiredExtension, unsigned NF)
768+
const std::vector<StringRef> &RequiredExtensions,
769+
unsigned NF)
768770
: IRName(IRName), IsMask(IsMask), HasVL(HasVL), HasPolicy(HasPolicy),
769771
HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef),
770772
ManualCodegen(ManualCodegen.str()), NF(NF) {
@@ -794,8 +796,12 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
794796
else if (T->isFloatVector(64) || T->isFloat(64))
795797
RISCVExtensions |= RISCVExtension::D;
796798
}
797-
if (RequiredExtension == "Zvlsseg")
798-
RISCVExtensions |= RISCVExtension::Zvlsseg;
799+
for (auto Extension : RequiredExtensions) {
800+
if (Extension == "Zvlsseg")
801+
RISCVExtensions |= RISCVExtension::Zvlsseg;
802+
if (Extension == "RV64")
803+
RISCVExtensions |= RISCVExtension::RV64;
804+
}
799805

800806
// Init OutputType and InputTypes
801807
OutputType = OutInTypes[0];
@@ -1141,7 +1147,8 @@ void RVVEmitter::createRVVIntrinsics(
11411147
StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask");
11421148
std::vector<int64_t> IntrinsicTypes =
11431149
R->getValueAsListOfInts("IntrinsicTypes");
1144-
StringRef RequiredExtension = R->getValueAsString("RequiredExtension");
1150+
std::vector<StringRef> RequiredExtensions =
1151+
R->getValueAsListOfStrings("RequiredExtensions");
11451152
StringRef IRName = R->getValueAsString("IRName");
11461153
StringRef IRNameMask = R->getValueAsString("IRNameMask");
11471154
unsigned NF = R->getValueAsInt("NF");
@@ -1209,7 +1216,7 @@ void RVVEmitter::createRVVIntrinsics(
12091216
Name, SuffixStr, MangledName, MangledSuffixStr, IRName,
12101217
/*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, HasPolicy,
12111218
HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, Types.getValue(),
1212-
IntrinsicTypes, RequiredExtension, NF));
1219+
IntrinsicTypes, RequiredExtensions, NF));
12131220
if (HasMask) {
12141221
// Create a mask intrinsic
12151222
Optional<RVVTypes> MaskTypes =
@@ -1218,7 +1225,7 @@ void RVVEmitter::createRVVIntrinsics(
12181225
Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask,
12191226
/*IsMask=*/true, HasMaskedOffOperand, HasVL, HasPolicy,
12201227
HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask,
1221-
MaskTypes.getValue(), IntrinsicTypes, RequiredExtension, NF));
1228+
MaskTypes.getValue(), IntrinsicTypes, RequiredExtensions, NF));
12221229
}
12231230
} // end for Log2LMULList
12241231
} // end for TypeRange
@@ -1306,6 +1313,8 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
13061313
OS << LS << "defined(__riscv_zfh)";
13071314
if (Extents & RISCVExtension::Zvlsseg)
13081315
OS << LS << "defined(__riscv_zvlsseg)";
1316+
if (Extents & RISCVExtension::RV64)
1317+
OS << LS << "(__riscv_xlen == 64)";
13091318
OS << "\n";
13101319
return true;
13111320
}

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,10 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
397397

398398
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
399399
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
400+
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
401+
report_fatal_error("The V extension does not support EEW=64 for index "
402+
"values when XLEN=32");
403+
}
400404
const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(
401405
NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
402406
static_cast<unsigned>(IndexLMUL));
@@ -475,6 +479,10 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
475479

476480
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
477481
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
482+
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
483+
report_fatal_error("The V extension does not support EEW=64 for index "
484+
"values when XLEN=32");
485+
}
478486
const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(
479487
NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
480488
static_cast<unsigned>(IndexLMUL));
@@ -1128,6 +1136,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
11281136
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
11291137
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
11301138
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
1139+
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
1140+
report_fatal_error("The V extension does not support EEW=64 for index "
1141+
"values when XLEN=32");
1142+
}
11311143
const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo(
11321144
IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
11331145
static_cast<unsigned>(IndexLMUL));
@@ -1318,6 +1330,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
13181330
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
13191331
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
13201332
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
1333+
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
1334+
report_fatal_error("The V extension does not support EEW=64 for index "
1335+
"values when XLEN=32");
1336+
}
13211337
const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo(
13221338
IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
13231339
static_cast<unsigned>(IndexLMUL));

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5538,6 +5538,11 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
55385538
}
55395539
}
55405540

5541+
if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) {
5542+
IndexVT = IndexVT.changeVectorElementType(XLenVT);
5543+
Index = DAG.getNode(ISD::TRUNCATE, DL, IndexVT, Index);
5544+
}
5545+
55415546
if (!VL)
55425547
VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
55435548

@@ -5639,6 +5644,11 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op,
56395644
}
56405645
}
56415646

5647+
if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) {
5648+
IndexVT = IndexVT.changeVectorElementType(XLenVT);
5649+
Index = DAG.getNode(ISD::TRUNCATE, DL, IndexVT, Index);
5650+
}
5651+
56425652
if (!VL)
56435653
VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
56445654

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -801,6 +801,10 @@ foreach eew = [8, 16, 32, 64] in {
801801
// Vector Strided Instructions
802802
def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSched<eew>;
803803
def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSched<eew>;
804+
}
805+
806+
foreach eew = [8, 16, 32] in {
807+
defvar w = !cast<RISCVWidth>("LSWidth" # eew);
804808

805809
// Vector Indexed Instructions
806810
def VLUXEI#eew#_V :
@@ -812,7 +816,21 @@ foreach eew = [8, 16, 32, 64] in {
812816
def VSOXEI#eew#_V :
813817
VIndexedStore<MOPSTIndexedOrder, w, "vsoxei"#eew#".v">, VSXSched<eew, "O">;
814818
}
819+
} // Predicates = [HasStdExtV]
815820

821+
let Predicates = [HasStdExtV, IsRV64] in {
822+
// Vector Indexed Instructions
823+
def VLUXEI64_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth64, "vluxei64.v">,
824+
VLXSched<64, "U">;
825+
def VLOXEI64_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth64, "vloxei64.v">,
826+
VLXSched<64, "O">;
827+
def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">,
828+
VSXSched<64, "U">;
829+
def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">,
830+
VSXSched<64, "O">;
831+
} // Predicates = [HasStdExtV, IsRV64]
832+
833+
let Predicates = [HasStdExtV] in {
816834
def VLM_V : VUnitStrideLoadMask<"vlm.v">,
817835
Sched<[WriteVLDM, ReadVLDX]>;
818836
def VSM_V : VUnitStrideStoreMask<"vsm.v">,
@@ -1430,6 +1448,10 @@ let Predicates = [HasStdExtZvlsseg] in {
14301448
VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">;
14311449
def VSSSEG#nf#E#eew#_V :
14321450
VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">;
1451+
}
1452+
1453+
foreach eew = [8, 16, 32] in {
1454+
defvar w = !cast<RISCVWidth>("LSWidth"#eew);
14331455

14341456
// Vector Indexed Instructions
14351457
def VLUXSEG#nf#EI#eew#_V :
@@ -1448,4 +1470,22 @@ let Predicates = [HasStdExtZvlsseg] in {
14481470
}
14491471
} // Predicates = [HasStdExtZvlsseg]
14501472

1473+
let Predicates = [HasStdExtZvlsseg, IsRV64] in {
1474+
foreach nf=2-8 in {
1475+
// Vector Indexed Instructions
1476+
def VLUXSEG#nf#EI64_V :
1477+
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64,
1478+
"vluxseg"#nf#"ei64.v">;
1479+
def VLOXSEG#nf#EI64_V :
1480+
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64,
1481+
"vloxseg"#nf#"ei64.v">;
1482+
def VSUXSEG#nf#EI64_V :
1483+
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
1484+
"vsuxseg"#nf#"ei64.v">;
1485+
def VSOXSEG#nf#EI64_V :
1486+
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
1487+
"vsoxseg"#nf#"ei64.v">;
1488+
}
1489+
} // Predicates = [HasStdExtZvlsseg, IsRV64]
1490+
14511491
include "RISCVInstrInfoVPseudos.td"

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