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Simon Moll
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[VE] vp_select+vectorBinOp passthru isel and tests
Extend the VE binaryop vector isel patterns to use passthru when the result of a SDNode is used in a vector select or merge. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D117495
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5 files changed

+411
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‎llvm/lib/Target/VE/VVPInstrPatternsVec.td

Lines changed: 49 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,22 @@ include "VVPInstrInfo.td"
2020
multiclass Binary_rv<SDPatternOperator OpNode,
2121
ValueType ScalarVT, ValueType DataVT,
2222
ValueType MaskVT, string OpBaseName> {
23-
// Masked with select, broadcast.
24-
// TODO
23+
// Masked with passthru, broadcast.
24+
def : Pat<(vvp_select
25+
(OpNode
26+
(any_broadcast ScalarVT:$sx),
27+
DataVT:$vy,
28+
(MaskVT srcvalue),
29+
(i32 srcvalue)),
30+
DataVT:$vfalse,
31+
MaskVT:$mask,
32+
i32:$pivot),
33+
(!cast<Instruction>(OpBaseName#"rvml_v")
34+
ScalarVT:$sx,
35+
$vy,
36+
$mask,
37+
$pivot,
38+
$vfalse)>;
2539

2640
// Unmasked, broadcast.
2741
def : Pat<(OpNode
@@ -42,8 +56,22 @@ multiclass Binary_rv<SDPatternOperator OpNode,
4256
multiclass Binary_vr<SDPatternOperator OpNode,
4357
ValueType ScalarVT, ValueType DataVT,
4458
ValueType MaskVT, string OpBaseName> {
45-
// Masked with select, broadcast.
46-
// TODO
59+
// Masked with passthru, broadcast.
60+
def : Pat<(vvp_select
61+
(OpNode
62+
DataVT:$vx,
63+
(any_broadcast ScalarVT:$sy),
64+
(MaskVT srcvalue),
65+
(i32 srcvalue)),
66+
DataVT:$vfalse,
67+
MaskVT:$mask,
68+
i32:$pivot),
69+
(!cast<Instruction>(OpBaseName#"vrml_v")
70+
$vx,
71+
ScalarVT:$sy,
72+
$mask,
73+
$pivot,
74+
$vfalse)>;
4775

4876
// Unmasked, broadcast.
4977
def : Pat<(OpNode
@@ -64,6 +92,23 @@ multiclass Binary_vr<SDPatternOperator OpNode,
6492
multiclass Binary_vv<SDPatternOperator OpNode,
6593
ValueType DataVT,
6694
ValueType MaskVT, string OpBaseName> {
95+
// Masked with passthru, broadcast.
96+
def : Pat<(vvp_select
97+
(OpNode
98+
DataVT:$vx,
99+
DataVT:$vy,
100+
(MaskVT srcvalue),
101+
(i32 srcvalue)),
102+
DataVT:$vfalse,
103+
MaskVT:$mask,
104+
i32:$pivot),
105+
(!cast<Instruction>(OpBaseName#"vvml_v")
106+
$vx,
107+
$vy,
108+
$mask,
109+
$pivot,
110+
$vfalse)>;
111+
67112
// Masked with select.
68113
// TODO
69114

‎llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
5+
declare <256 x float> @llvm.vp.fadd.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
6+
7+
define fastcc <256 x float> @test_vp_fadd_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
8+
; CHECK-LABEL: test_vp_fadd_v256f32_vv_merge:
9+
; CHECK: # %bb.0:
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: lvl %s0
12+
; CHECK-NEXT: pvfadd.up %v0, %v1, %v2, %vm1
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
15+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
16+
ret <256 x float> %r0
17+
}
18+
19+
define fastcc <256 x float> @test_vp_fadd_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fadd_v256f32_rv_merge:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s1, %s1, (32)0
23+
; CHECK-NEXT: lvl %s1
24+
; CHECK-NEXT: pvfadd.up %v0, %s0, %v1, %vm1
25+
; CHECK-NEXT: b.l.t (, %s10)
26+
%xins = insertelement <256 x float> undef, float %s0, i32 0
27+
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
28+
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
29+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
30+
ret <256 x float> %r0
31+
}
32+
33+
define fastcc <256 x float> @test_vp_fadd_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
34+
; CHECK-LABEL: test_vp_fadd_v256f32_vr_merge:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: and %s1, %s1, (32)0
37+
; CHECK-NEXT: lvl %s1
38+
; CHECK-NEXT: pvfadd.up %v0, %s0, %v1, %vm1
39+
; CHECK-NEXT: b.l.t (, %s10)
40+
%yins = insertelement <256 x float> undef, float %s1, i32 0
41+
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
42+
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
43+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
44+
ret <256 x float> %r0
45+
}
46+
47+
48+
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
49+
declare <256 x double> @llvm.vp.fadd.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
50+
51+
define fastcc <256 x double> @test_vp_fadd_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
52+
; CHECK-LABEL: test_vp_fadd_v256f64_vv_merge:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: and %s0, %s0, (32)0
55+
; CHECK-NEXT: lvl %s0
56+
; CHECK-NEXT: vfadd.d %v0, %v1, %v2, %vm1
57+
; CHECK-NEXT: b.l.t (, %s10)
58+
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
59+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
60+
ret <256 x double> %r0
61+
}
62+
63+
define fastcc <256 x double> @test_vp_fadd_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
64+
; CHECK-LABEL: test_vp_fadd_v256f64_rv_merge:
65+
; CHECK: # %bb.0:
66+
; CHECK-NEXT: and %s1, %s1, (32)0
67+
; CHECK-NEXT: lvl %s1
68+
; CHECK-NEXT: vfadd.d %v0, %s0, %v1, %vm1
69+
; CHECK-NEXT: b.l.t (, %s10)
70+
%xins = insertelement <256 x double> undef, double %s0, i32 0
71+
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
72+
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
73+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
74+
ret <256 x double> %r0
75+
}
76+
77+
define fastcc <256 x double> @test_vp_fadd_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
78+
; CHECK-LABEL: test_vp_fadd_v256f64_vr_merge:
79+
; CHECK: # %bb.0:
80+
; CHECK-NEXT: and %s1, %s1, (32)0
81+
; CHECK-NEXT: lvl %s1
82+
; CHECK-NEXT: vfadd.d %v0, %s0, %v1, %vm1
83+
; CHECK-NEXT: b.l.t (, %s10)
84+
%yins = insertelement <256 x double> undef, double %s1, i32 0
85+
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
86+
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
87+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
88+
ret <256 x double> %r0
89+
}

‎llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
5+
declare <256 x float> @llvm.vp.fdiv.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
6+
7+
define fastcc <256 x float> @test_vp_fdiv_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
8+
; CHECK-LABEL: test_vp_fdiv_v256f32_vv_merge:
9+
; CHECK: # %bb.0:
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: lvl %s0
12+
; CHECK-NEXT: vfdiv.s %v0, %v1, %v2, %vm1
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
15+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
16+
ret <256 x float> %r0
17+
}
18+
19+
define fastcc <256 x float> @test_vp_fdiv_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fdiv_v256f32_rv_merge:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s1, %s1, (32)0
23+
; CHECK-NEXT: lvl %s1
24+
; CHECK-NEXT: vfdiv.s %v0, %s0, %v1, %vm1
25+
; CHECK-NEXT: b.l.t (, %s10)
26+
%xins = insertelement <256 x float> undef, float %s0, i32 0
27+
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
28+
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
29+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
30+
ret <256 x float> %r0
31+
}
32+
33+
define fastcc <256 x float> @test_vp_fdiv_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
34+
; CHECK-LABEL: test_vp_fdiv_v256f32_vr_merge:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: and %s1, %s1, (32)0
37+
; CHECK-NEXT: lvl %s1
38+
; CHECK-NEXT: vfdiv.s %v0, %v1, %s0, %vm1
39+
; CHECK-NEXT: b.l.t (, %s10)
40+
%yins = insertelement <256 x float> undef, float %s1, i32 0
41+
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
42+
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
43+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
44+
ret <256 x float> %r0
45+
}
46+
47+
48+
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
49+
declare <256 x double> @llvm.vp.fdiv.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
50+
51+
define fastcc <256 x double> @test_vp_fdiv_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
52+
; CHECK-LABEL: test_vp_fdiv_v256f64_vv_merge:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: and %s0, %s0, (32)0
55+
; CHECK-NEXT: lvl %s0
56+
; CHECK-NEXT: vfdiv.d %v0, %v1, %v2, %vm1
57+
; CHECK-NEXT: b.l.t (, %s10)
58+
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
59+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
60+
ret <256 x double> %r0
61+
}
62+
63+
define fastcc <256 x double> @test_vp_fdiv_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
64+
; CHECK-LABEL: test_vp_fdiv_v256f64_rv_merge:
65+
; CHECK: # %bb.0:
66+
; CHECK-NEXT: and %s1, %s1, (32)0
67+
; CHECK-NEXT: lvl %s1
68+
; CHECK-NEXT: vfdiv.d %v0, %s0, %v1, %vm1
69+
; CHECK-NEXT: b.l.t (, %s10)
70+
%xins = insertelement <256 x double> undef, double %s0, i32 0
71+
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
72+
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
73+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
74+
ret <256 x double> %r0
75+
}
76+
77+
define fastcc <256 x double> @test_vp_fdiv_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
78+
; CHECK-LABEL: test_vp_fdiv_v256f64_vr_merge:
79+
; CHECK: # %bb.0:
80+
; CHECK-NEXT: and %s1, %s1, (32)0
81+
; CHECK-NEXT: lvl %s1
82+
; CHECK-NEXT: vfdiv.d %v0, %v1, %s0, %vm1
83+
; CHECK-NEXT: b.l.t (, %s10)
84+
%yins = insertelement <256 x double> undef, double %s1, i32 0
85+
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
86+
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
87+
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
88+
ret <256 x double> %r0
89+
}

‎llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
5+
declare <256 x float> @llvm.vp.fmul.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
6+
7+
define fastcc <256 x float> @test_vp_fmul_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
8+
; CHECK-LABEL: test_vp_fmul_v256f32_vv_merge:
9+
; CHECK: # %bb.0:
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: lvl %s0
12+
; CHECK-NEXT: pvfmul.up %v0, %v1, %v2, %vm1
13+
; CHECK-NEXT: b.l.t (, %s10)
14+
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
15+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
16+
ret <256 x float> %r0
17+
}
18+
19+
define fastcc <256 x float> @test_vp_fmul_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fmul_v256f32_rv_merge:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s1, %s1, (32)0
23+
; CHECK-NEXT: lvl %s1
24+
; CHECK-NEXT: pvfmul.up %v0, %s0, %v1, %vm1
25+
; CHECK-NEXT: b.l.t (, %s10)
26+
%xins = insertelement <256 x float> undef, float %s0, i32 0
27+
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
28+
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
29+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
30+
ret <256 x float> %r0
31+
}
32+
33+
define fastcc <256 x float> @test_vp_fmul_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
34+
; CHECK-LABEL: test_vp_fmul_v256f32_vr_merge:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: and %s1, %s1, (32)0
37+
; CHECK-NEXT: lvl %s1
38+
; CHECK-NEXT: pvfmul.up %v0, %s0, %v1, %vm1
39+
; CHECK-NEXT: b.l.t (, %s10)
40+
%yins = insertelement <256 x float> undef, float %s1, i32 0
41+
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
42+
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
43+
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
44+
ret <256 x float> %r0
45+
}
46+
47+
48+
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
49+
declare <256 x double> @llvm.vp.fmul.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
50+
51+
define fastcc <256 x double> @test_vp_fmul_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
52+
; CHECK-LABEL: test_vp_fmul_v256f64_vv_merge:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: and %s0, %s0, (32)0
55+
; CHECK-NEXT: lvl %s0
56+
; CHECK-NEXT: vfmul.d %v0, %v1, %v2, %vm1
57+
; CHECK-NEXT: b.l.t (, %s10)
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%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
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%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
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ret <256 x double> %r0
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}
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define fastcc <256 x double> @test_vp_fmul_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fmul_v256f64_rv_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmul.d %v0, %s0, %v1, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x double> undef, double %s0, i32 0
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%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
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%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
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%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
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ret <256 x double> %r0
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}
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define fastcc <256 x double> @test_vp_fmul_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fmul_v256f64_vr_merge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vfmul.d %v0, %s0, %v1, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x double> undef, double %s1, i32 0
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%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
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%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
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%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
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ret <256 x double> %r0
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}

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