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Merge pull request #139 from sx-aurora-dev/merge/vp_merge
Merge/vp merge
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llvm/docs/LangRef.rst

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@@ -17856,6 +17856,67 @@ Example:
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%also.r = select <4 x i1> %cond, <4 x i32> %on_true, <4 x i32> %on_false
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.. _int_vp_merge:
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'``llvm.vp.merge.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.merge.v16i32 (<16 x i1> <condition>, <16 x i32> <on_true>, <16 x i32> <on_false>, i32 <pivot>)
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declare <vscale x 4 x i64> @llvm.vp.merge.nxv4i64 (<vscale x 4 x i1> <condition>, <vscale x 4 x i64> <on_true>, <vscale x 4 x i64> <on_false>, i32 <pivot>)
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Overview:
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"""""""""
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The '``llvm.vp.merge``' intrinsic is used to choose one value based on a
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condition vector and an index operand, without IR-level branching.
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Arguments:
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""""""""""
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The first operand is a vector of ``i1`` and indicates the condition. The
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second operand is the value that is merged where the condition vector is true.
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The third operand is the value that is selected where the condition vector is
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false or the lane position is greater equal than the pivot. The fourth operand
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is the pivot.
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#. The optional ``fast-math flags`` marker indicates that the merge has one or
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more :ref:`fast-math flags <fastmath>`. These are optimization hints to
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enable otherwise unsafe floating-point optimizations. Fast-math flags are
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only valid for merges that return a floating-point scalar or vector type,
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or an array (nested to any depth) of floating-point scalar or vector types.
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Semantics:
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""""""""""
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The intrinsic selects lanes from the second and third operand depending on a
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condition vector and pivot value.
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For all lanes where the condition vector is true and the lane position is less
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than ``%pivot`` the lane is taken from the second operand. Otherwise, the lane
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is taken from the third operand.
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Example:
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""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.merge.v4i32(<4 x i1> %cond, <4 x i32> %on_true, <4 x i32> %on_false, i32 %pivot)
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;;; Expansion.
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;; Lanes at and above %pivot are taken from %on_false
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%atfirst = insertelement <4 x i32> undef, i32 %pivot, i32 0
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%splat = shufflevector <4 x i32> %atfirst, <4 x i32> poison, <4 x i32> zeroinitializer
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%pivotmask = icmp ult <4 x i32> %splat, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%mergemask = and <4 x i1> %cond, <4 x i1> %pivotmask
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%also.r = select <4 x i1> %mergemask, <4 x i32> %on_true, <4 x i32> %on_false
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.. _int_vp_add:
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llvm/include/llvm/IR/Intrinsics.td

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@@ -1695,6 +1695,12 @@ def int_vp_fma : Intrinsic<[ llvm_anyvector_ty ],
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[ IntrNoMem, IntrNoSync, IntrWillReturn]>;
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def int_vp_merge : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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LLVMMatchType<0>,
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LLVMMatchType<0>,
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llvm_i32_ty]>;
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// Reductions
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let IntrProperties = [IntrSpeculatable, IntrNoMem, IntrNoSync, IntrWillReturn] in {
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def int_vp_reduce_fadd : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],

llvm/include/llvm/IR/VPIntrinsics.def

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@@ -612,6 +612,10 @@ BEGIN_REGISTER_VP_INTRINSIC(vp_vshift, 2, 3)
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BEGIN_REGISTER_VP_SDNODE(VP_VSHIFT, -1, vp_vshift, 2, 3)
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END_REGISTER_CASES(vp_vshift, VP_VSHIFT)
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// llvm.vp.merge(mask,on_true,on_false,pivot)
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BEGIN_REGISTER_VP(vp_merge, 0, 3, VP_MERGE, -1)
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END_REGISTER_VP(vp_merge, VP_MERGE)
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BEGIN_REGISTER_VP(experimental_vp_splice, 3, 5, EXPERIMENTAL_VP_SPLICE, -1)
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END_REGISTER_VP(experimental_vp_splice, EXPERIMENTAL_VP_SPLICE)
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llvm/lib/IR/IntrinsicInst.cpp

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@@ -593,6 +593,7 @@ static VPIntrinsic::ShortTypeVec getVPIntrinsicTypes(Intrinsic::ID ID,
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case Intrinsic::vp_vshift:
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return VPIntrinsic::ShortTypeVec{VectorTy};
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case Intrinsic::vp_merge:
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case Intrinsic::vp_select:
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case Intrinsic::experimental_vp_splice:
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case Intrinsic::vp_compress:

llvm/unittests/IR/VPIntrinsicTest.cpp

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@@ -116,6 +116,8 @@ class VPIntrinsicTest : public testing::Test {
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Str << " declare float @llvm.vp.reduce." << ReductionOpcode
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<< ".v8f32(float, <8 x float>, <8 x i1>, i32) ";
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Str << " declare <8 x i32> @llvm.vp.merge.v8i32(<8 x i1>, <8 x i32>, <8 x "
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"i32>, i32)";
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Str << " declare <8 x i32> @llvm.vp.select.v8i32(<8 x i1>, <8 x i32>, <8 x "
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"i32>, i32)";
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Str << " declare <8 x i32> @llvm.experimental.vp.splice.v8i32(<8 x "

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