From 4f74a923036eac47b8ca35f5c74159ea7c630e58 Mon Sep 17 00:00:00 2001
From: Jonas Spanoghe <jonas@spanoghe.net>
Date: Tue, 19 Apr 2022 21:29:21 +0200
Subject: [PATCH 1/2] Configure GPIOx_ASCR register for STM32L47x/STM32L48x

---
 src/gpio/convert.rs | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/gpio/convert.rs b/src/gpio/convert.rs
index d9621147..4d129ce5 100644
--- a/src/gpio/convert.rs
+++ b/src/gpio/convert.rs
@@ -150,6 +150,26 @@ impl<MODE, HL, const P: char, const N: u8> Pin<MODE, HL, P, N> {
         _pupdr: &mut PUPDR<P>,
     ) -> Pin<Analog, HL, P, N> {
         self.mode::<Analog>();
+
+        #[cfg(any(
+            feature = "stm32l471",
+            feature = "stm32l475",
+            feature = "stm32l476",
+            feature = "stm32l485",
+            feature = "stm32l486",
+        ))]
+        {
+            // On STM32L47x/L48x devices, before any conversion of an input channel coming from
+            // GPIO pads, it is necessary to configure the corresponding GPIOx_ASCR register
+            // in the GPIO, in addition to the I/O configuration in analog mode.
+            let offset = { N };
+            unsafe {
+                (*Gpio::<P>::ptr())
+                    .ascr
+                    .modify(|r, w| w.bits(r.bits() | (1 << offset)))
+            };
+        }
+
         Pin::new()
     }
 

From e74297a91dbc068c185b32d29f12d356c88c5e08 Mon Sep 17 00:00:00 2001
From: Jonas Spanoghe <jonas@spanoghe.net>
Date: Sun, 10 Jul 2022 10:01:37 +0200
Subject: [PATCH 2/2] Update PAC `stm32l4` to v0.15.1

---
 Cargo.toml      |  2 +-
 src/pwm.rs      |  4 ++--
 src/rtc.rs      |  4 ++--
 src/tsc.rs      |  2 +-
 src/watchdog.rs | 27 ---------------------------
 5 files changed, 6 insertions(+), 33 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index 692c72bf..72617a9b 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -23,7 +23,7 @@ edition = "2018"
 [dependencies]
 cortex-m = "0.7"
 nb = "0.1.1"
-stm32l4 = "0.14.0"
+stm32l4 = "0.15.1"
 embedded-dma = "0.1"
 bxcan = ">=0.4, <0.7"
 fugit = "0.3.5"
diff --git a/src/pwm.rs b/src/pwm.rs
index 2c371bb0..e96c5c26 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -370,7 +370,7 @@ macro_rules! pwm_channels {
 
                 #[inline(always)]
                 fn get_duty(&self) -> Self::Duty {
-                    unsafe { (*$TIMX::ptr()).$ccrX.read().$ccr().bits() }
+                    unsafe { (*$TIMX::ptr()).$ccrX().read().$ccr().bits() }
                 }
 
                 #[inline(always)]
@@ -380,7 +380,7 @@ macro_rules! pwm_channels {
 
                 #[inline(always)]
                 fn set_duty(&mut self, duty: Self::Duty) {
-                    unsafe { (*$TIMX::ptr()).$ccrX.write(|w| w.$ccr().bits(duty)) }
+                    unsafe { (*$TIMX::ptr()).$ccrX().write(|w| w.$ccr().bits(duty)) }
                 }
             }
         )+
diff --git a/src/rtc.rs b/src/rtc.rs
index 944a0744..a077eb39 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -271,7 +271,7 @@ impl Rtc {
                 rtc_registers::clear_alarm_a_flag(rtc);
                 while !rtc_registers::is_alarm_a_accessible(rtc) {}
 
-                rtc.alrmar.modify(|_, w| unsafe {
+                rtc.alrmar().modify(|_, w| unsafe {
                     w.dt()
                         .bits(dt)
                         .du()
@@ -307,7 +307,7 @@ impl Rtc {
                 rtc_registers::clear_alarm_b_flag(rtc);
                 while !rtc_registers::is_alarm_b_accessible(rtc) {}
 
-                rtc.alrmbr.modify(|_, w| unsafe {
+                rtc.alrmbr().modify(|_, w| unsafe {
                     w.dt()
                         .bits(dt)
                         .du()
diff --git a/src/tsc.rs b/src/tsc.rs
index 4cef1085..10278e7e 100644
--- a/src/tsc.rs
+++ b/src/tsc.rs
@@ -267,7 +267,7 @@ impl<SPIN> Tsc<SPIN> {
     /// Reads the tsc group 2 count register
     /// WARNING, just returns the contents of the register! No validation of the correct pin
     pub fn read_unchecked(&self) -> u16 {
-        self.tsc.iog2cr.read().cnt().bits()
+        self.tsc.iog2cr().read().cnt().bits()
     }
 
     /// Is the tsc performing an aquisition
diff --git a/src/watchdog.rs b/src/watchdog.rs
index de60d9c9..52762374 100644
--- a/src/watchdog.rs
+++ b/src/watchdog.rs
@@ -27,34 +27,7 @@ impl IndependentWatchdog {
 
     /// Debug independent watchdog stopped when core is halted
     pub fn stop_on_debug(&self, dbgmcu: &DBGMCU, stop: bool) {
-        #[cfg(any(
-            feature = "stm32l431",
-            feature = "stm32l451",
-            feature = "stm32l471",
-            feature = "stm32l412",
-            feature = "stm32l422",
-            feature = "stm32l432",
-            feature = "stm32l442",
-            feature = "stm32l452",
-            feature = "stm32l462",
-            feature = "stm32l433",
-            feature = "stm32l443",
-        ))]
         dbgmcu.apb1fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
-        #[cfg(not(any(
-            feature = "stm32l431",
-            feature = "stm32l451",
-            feature = "stm32l471",
-            feature = "stm32l412",
-            feature = "stm32l422",
-            feature = "stm32l432",
-            feature = "stm32l442",
-            feature = "stm32l452",
-            feature = "stm32l462",
-            feature = "stm32l433",
-            feature = "stm32l443",
-        )))]
-        dbgmcu.apb1_fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
     }
 
     /// Sets the watchdog timer timout period. Max: 32768 ms