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Use new dmamux interface in adc.rs, serial.rs and spi.rs
1 parent 2990768 commit b8899ae

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3 files changed

+22
-25
lines changed

3 files changed

+22
-25
lines changed

‎src/adc.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ use core::{
88

99
use crate::{
1010
dma::{dma1, Event as DMAEvent, RxDma, Transfer, TransferPayload, W},
11+
dmamux::{DmaInput, DmaMux},
1112
gpio::{self, Analog},
1213
hal::{
1314
adc::{Channel as EmbeddedHalChannel, OneShot},
@@ -523,7 +524,7 @@ where
523524
channel.set_memory_address(buffer.as_ptr() as u32, true);
524525
channel.set_transfer_length(N as u16);
525526

526-
channel.cselr().modify(|_, w| w.c1s().bits(0b0000));
527+
channel.set_request_line(DmaInput::Adc1).unwrap();
527528

528529
channel.ccr().modify(|_, w| unsafe {
529530
w.mem2mem()

‎src/serial.rs

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ use crate::dma::{
1616
dma1, CircBuffer, DMAFrame, FrameReader, FrameSender, Receive, RxDma, TransferPayload,
1717
Transmit, TxDma,
1818
};
19+
use crate::dmamux::{DmaInput, DmaMux};
1920
use crate::gpio::{self, Alternate, OpenDrain, PushPull};
2021
use crate::pac;
2122
use crate::rcc::{Clocks, Enable, RccBus, Reset};
@@ -216,8 +217,8 @@ macro_rules! hal {
216217
$USARTX:ident: (
217218
$usartX:ident,
218219
$pclkX:ident,
219-
tx: ($txdma:ident, $dmacst:ident, $dmatxch:path),
220-
rx: ($rxdma:ident, $dmacsr:ident, $dmarxch:path)
220+
tx: ($txdma:ident, $dmatxch:path, $dmatxsel:path),
221+
rx: ($rxdma:ident, $dmarxch:path, $dmarxsel:path)
221222
),
222223
)+) => {
223224
$(
@@ -710,9 +711,7 @@ macro_rules! hal {
710711
self.channel.set_transfer_length(len as u16);
711712

712713
// Tell DMA to request from serial
713-
self.channel.cselr().modify(|_, w| {
714-
w.$dmacsr().map2()
715-
});
714+
self.channel.set_request_line($dmarxsel).unwrap();
716715

717716
self.channel.ccr().modify(|_, w| {
718717
w
@@ -765,9 +764,7 @@ macro_rules! hal {
765764
self.channel.set_transfer_length(buf.max_len() as u16);
766765

767766
// Tell DMA to request from serial
768-
self.channel.cselr().modify(|_, w| {
769-
w.$dmacsr().map2()
770-
});
767+
self.channel.set_request_line($dmarxsel).unwrap();
771768

772769
self.channel.ccr().modify(|_, w| {
773770
w
@@ -812,9 +809,7 @@ macro_rules! hal {
812809
self.channel.set_peripheral_address(&usart.tdr as *const _ as u32, false);
813810

814811
// Tell DMA to request from serial
815-
self.channel.cselr().modify(|_, w| {
816-
w.$dmacst().map2()
817-
});
812+
self.channel.set_request_line($dmatxsel).unwrap();
818813

819814
self.channel.ccr().modify(|_, w| unsafe {
820815
w.mem2mem()
@@ -841,13 +836,13 @@ macro_rules! hal {
841836
}
842837

843838
hal! {
844-
USART1: (usart1, pclk2, tx: (TxDma1, c4s, dma1::C4), rx: (RxDma1, c5s, dma1::C5)),
845-
USART2: (usart2, pclk1, tx: (TxDma2, c7s, dma1::C7), rx: (RxDma2, c6s, dma1::C6)),
839+
USART1: (usart1, pclk2, tx: (TxDma1, dma1::C4, DmaInput::Usart1Tx), rx: (RxDma1, dma1::C5, DmaInput::Usart1Rx)),
840+
USART2: (usart2, pclk1, tx: (TxDma2, dma1::C7, DmaInput::Usart2Tx), rx: (RxDma2, dma1::C6, DmaInput::Usart2Rx)),
846841
}
847842

848843
#[cfg(not(any(feature = "stm32l432", feature = "stm32l442")))]
849844
hal! {
850-
USART3: (usart3, pclk1, tx: (TxDma3, c2s, dma1::C2), rx: (RxDma3, c3s, dma1::C3)),
845+
USART3: (usart3, pclk1, tx: (TxDma3, dma1::C2, DmaInput::Usart3Tx), rx: (RxDma3, dma1::C3, DmaInput::Usart3Rx)),
851846
}
852847

853848
#[cfg(any(
@@ -871,7 +866,7 @@ hal! {
871866
feature = "stm32l4s9",
872867
))]
873868
hal! {
874-
UART4: (uart4, pclk1, tx: (TxDma4, c3s, dma2::C3), rx: (RxDma4, c5s, dma2::C5)),
869+
UART4: (uart4, pclk1, tx: (TxDma4, dma2::C3, DmaInput::Uart4Tx), rx: (RxDma4, dma2::C5, DmaInput::Uart4Rx)),
875870
}
876871

877872
#[cfg(any(
@@ -892,7 +887,7 @@ hal! {
892887
feature = "stm32l4s9",
893888
))]
894889
hal! {
895-
UART5: (uart5, pclk1, tx: (TxDma5, c1s, dma2::C1), rx: (RxDma5, c2s, dma2::C2)),
890+
UART5: (uart5, pclk1, tx: (TxDma5, dma2::C1, DmaInput::Uart5Tx), rx: (RxDma5, dma2::C2, DmaInput::Uart5Rx)),
896891
}
897892

898893
impl<USART, PINS> fmt::Write for Serial<USART, PINS>

‎src/spi.rs

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ use core::sync::atomic::Ordering;
1212
#[cfg(not(any(feature = "stm32l433", feature = "stm32l443",)))]
1313
use crate::dma::dma2;
1414
use crate::dma::{self, dma1, TransferPayload};
15+
use crate::dmamux::{DmaInput, DmaMux};
1516
use crate::gpio::{Alternate, PushPull};
1617
use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
1718
use crate::rcc::{Clocks, Enable, RccBus, Reset};
@@ -373,7 +374,7 @@ pub type SpiTxDma<SPI, PINS, CHANNEL> = dma::TxDma<SpiPayload<SPI, PINS>, CHANNE
373374
pub type SpiRxTxDma<SPI, PINS, RXCH, TXCH> = dma::RxTxDma<SpiPayload<SPI, PINS>, RXCH, TXCH>;
374375

375376
macro_rules! spi_dma {
376-
($SPIX:ident, $RX_CH:path, $RX_CHX:ident, $RX_MAPX:ident, $TX_CH:path, $TX_CHX:ident, $TX_MAPX:ident) => {
377+
($SPIX:ident, $RX_CH:path, $RX_CHSEL:path, $TX_CH:path, $TX_CHSEL:path) => {
377378
impl<PINS> dma::Receive for SpiRxDma<$SPIX, PINS, $RX_CH> {
378379
type RxChannel = $RX_CH;
379380
type TransmittedWord = u8;
@@ -400,7 +401,7 @@ macro_rules! spi_dma {
400401
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
401402
false,
402403
);
403-
channel.cselr().modify(|_, w| w.$RX_CHX().$RX_MAPX());
404+
channel.set_request_line($RX_CHSEL).unwrap();
404405
channel.ccr().modify(|_, w| {
405406
w
406407
// memory to memory mode disabled
@@ -435,7 +436,7 @@ macro_rules! spi_dma {
435436
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
436437
false,
437438
);
438-
channel.cselr().modify(|_, w| w.$TX_CHX().$TX_MAPX());
439+
channel.set_request_line($TX_CHSEL).unwrap();
439440
channel.ccr().modify(|_, w| {
440441
w
441442
// memory to memory mode disabled
@@ -477,7 +478,7 @@ macro_rules! spi_dma {
477478
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
478479
false,
479480
);
480-
rx_channel.cselr().modify(|_, w| w.$RX_CHX().$RX_MAPX());
481+
rx_channel.set_request_line($RX_CHSEL).unwrap();
481482

482483
rx_channel.ccr().modify(|_, w| {
483484
w
@@ -508,7 +509,7 @@ macro_rules! spi_dma {
508509
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
509510
false,
510511
);
511-
tx_channel.cselr().modify(|_, w| w.$TX_CHX().$TX_MAPX());
512+
tx_channel.set_request_line($TX_CHSEL).unwrap();
512513

513514
tx_channel.ccr().modify(|_, w| {
514515
w
@@ -768,7 +769,7 @@ macro_rules! spi_dma {
768769
};
769770
}
770771

771-
spi_dma!(SPI1, dma1::C2, c2s, map1, dma1::C3, c3s, map1);
772+
spi_dma!(SPI1, dma1::C2, DmaInput::Spi1Rx, dma1::C3, DmaInput::Spi1Tx);
772773
#[cfg(not(any(
773774
feature = "stm32l412",
774775
feature = "stm32l422",
@@ -777,7 +778,7 @@ spi_dma!(SPI1, dma1::C2, c2s, map1, dma1::C3, c3s, map1);
777778
feature = "stm32l452",
778779
feature = "stm32l462",
779780
)))]
780-
spi_dma!(SPI2, dma1::C4, c4s, map1, dma1::C5, c5s, map1);
781+
spi_dma!(SPI2, dma1::C4, DmaInput::Spi2Rx, dma1::C5, DmaInput::Spi2Tx);
781782
// spi_dma!(SPI1, dma2::C3, c3s, map4, dma2::C4, c4s, map4);
782783
#[cfg(not(any(feature = "stm32l433", feature = "stm32l443",)))]
783-
spi_dma!(SPI3, dma2::C1, c1s, map3, dma2::C2, c2s, map3);
784+
spi_dma!(SPI3, dma2::C1, DmaInput::Spi3Rx, dma2::C2, DmaInput::Spi3Tx);

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