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korken89korken89
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Merge pull request #268 from burrbull/rcc
rcc enable/reset unify
2 parents dc51e2d + 40f885e commit 9bc1940

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19 files changed

+454
-259
lines changed

19 files changed

+454
-259
lines changed

‎src/adc.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ use crate::{
1414
blocking::delay::DelayUs,
1515
},
1616
pac,
17-
rcc::{AHB2, CCIPR},
17+
rcc::{Enable, Reset, AHB2, CCIPR},
1818
signature::{VrefCal, VtempCal130, VtempCal30, VDDA_CALIB_MV},
1919
};
2020

@@ -130,11 +130,10 @@ impl ADC {
130130
delay: &mut impl DelayUs<u32>,
131131
) -> Self {
132132
// Enable peripheral
133-
ahb.enr().modify(|_, w| w.adcen().set_bit());
133+
ADC1::enable(ahb);
134134

135135
// Reset peripheral
136-
ahb.rstr().modify(|_, w| w.adcrst().set_bit());
137-
ahb.rstr().modify(|_, w| w.adcrst().clear_bit());
136+
ADC1::reset(ahb);
138137

139138
// Select system clock as ADC clock source
140139
ccipr.ccipr().modify(|_, w| {

‎src/can.rs

Lines changed: 10 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
//! Based on STM32F4xx HAL.
44
55
use crate::pac::CAN1;
6-
use crate::rcc::APB1R1;
6+
use crate::rcc::{Enable, RccBus, Reset};
77

88
mod sealed {
99
pub trait Sealed {}
@@ -55,43 +55,28 @@ mod pb13_pb12_af10 {
5555
pins! { CAN1 => (PB13<10>, PB12<10>), }
5656
}
5757

58-
/// Enable/disable peripheral
59-
pub trait Enable: sealed::Sealed {
60-
/// Enables this peripheral by setting the associated enable bit in an RCC enable register
61-
fn enable(apb: &mut APB1R1);
62-
}
63-
6458
impl crate::can::sealed::Sealed for crate::pac::CAN1 {}
6559

66-
impl crate::can::Enable for crate::pac::CAN1 {
67-
#[inline(always)]
68-
fn enable(apb: &mut APB1R1) {
69-
// Enable peripheral clock
70-
apb.enr().modify(|_, w| w.can1en().set_bit());
71-
apb.rstr().modify(|_, w| w.can1rst().set_bit());
72-
apb.rstr().modify(|_, w| w.can1rst().clear_bit());
73-
}
74-
}
75-
7660
/// Interface to the CAN peripheral.
77-
pub struct Can<Instance, Pins> {
78-
can: Instance,
61+
pub struct Can<CAN, Pins> {
62+
can: CAN,
7963
pins: Pins,
8064
}
8165

82-
impl<Instance, P> Can<Instance, P>
66+
impl<CAN, P> Can<CAN, P>
8367
where
84-
Instance: Enable,
85-
P: Pins<Instance = Instance>,
68+
CAN: Enable + Reset,
69+
P: Pins<Instance = CAN>,
8670
{
8771
/// Creates a CAN interface.
88-
pub fn new(apb: &mut APB1R1, can: Instance, pins: P) -> Can<Instance, P> {
89-
Instance::enable(apb);
72+
pub fn new(apb: &mut <CAN as RccBus>::Bus, can: CAN, pins: P) -> Can<CAN, P> {
73+
CAN::enable(apb);
74+
CAN::reset(apb);
9075
Can { can, pins }
9176
}
9277

9378
// Split the peripheral back into its components.
94-
pub fn split(self) -> (Instance, P) {
79+
pub fn split(self) -> (CAN, P) {
9580
(self.can, self.pins)
9681
}
9782
}

‎src/crc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
1717
#![deny(missing_docs)]
1818

19-
use crate::rcc;
19+
use crate::rcc::{self, Enable};
2020
use crate::stm32::CRC;
2121
use core::hash::Hasher;
2222

@@ -29,7 +29,7 @@ pub trait CrcExt {
2929
impl CrcExt for CRC {
3030
fn constrain(self, ahb1: &mut rcc::AHB1) -> Config {
3131
// Enable power to CRC unit
32-
ahb1.enr().modify(|_, w| w.crcen().set_bit());
32+
CRC::enable(ahb1);
3333

3434
// Default values
3535
Config {

‎src/dma.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -502,7 +502,7 @@ macro_rules! rx_tx_channel_mapping {
502502
}
503503

504504
macro_rules! dma {
505-
($($DMAX:ident: ($dmaX:ident, $dmaXen:ident, $dmaXrst:ident, {
505+
($($DMAX:ident: ($dmaX:ident, {
506506
$($CX:ident: (
507507
$ccrX:ident,
508508
$CCRX:ident,
@@ -530,7 +530,7 @@ macro_rules! dma {
530530
use stable_deref_trait::StableDeref;
531531

532532
use crate::dma::{CircBuffer, FrameReader, FrameSender, DMAFrame, DmaExt, Error, Event, Transfer, W, R, RW, RxDma, RxTxDma, TxDma, TransferPayload};
533-
use crate::rcc::AHB1;
533+
use crate::rcc::{AHB1, Enable};
534534

535535
#[allow(clippy::manual_non_exhaustive)]
536536
pub struct Channels((), $(pub $CX),+);
@@ -1070,7 +1070,7 @@ macro_rules! dma {
10701070
type Channels = Channels;
10711071

10721072
fn split(self, ahb: &mut AHB1) -> Channels {
1073-
ahb.enr().modify(|_, w| w.$dmaXen().set_bit());
1073+
<$DMAX>::enable(ahb);
10741074

10751075
// reset the DMA control registers (stops all on-going transfers)
10761076
$(
@@ -1086,7 +1086,7 @@ macro_rules! dma {
10861086
}
10871087

10881088
dma! {
1089-
DMA1: (dma1, dma1en, dma1rst, {
1089+
DMA1: (dma1, {
10901090
C1: (
10911091
ccr1, CCR1,
10921092
cndtr1, CNDTR1,
@@ -1151,7 +1151,7 @@ dma! {
11511151
teif7, cteif7
11521152
),
11531153
}),
1154-
DMA2: (dma2, dma2en, dma2rst, {
1154+
DMA2: (dma2, {
11551155
C1: (
11561156
ccr1, CCR1,
11571157
cndtr1, CNDTR1,

‎src/gpio.rs

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use core::convert::Infallible;
66
use core::marker::PhantomData;
77

88
use crate::pac::{self, EXTI, SYSCFG};
9-
use crate::rcc::{AHB2, APB2};
9+
use crate::rcc::{Enable, AHB2, APB2};
1010

1111
mod convert;
1212

@@ -105,7 +105,7 @@ where
105105
#[inline(always)]
106106
fn make_interrupt_source(&mut self, syscfg: &mut SYSCFG, apb2: &mut APB2) {
107107
// SYSCFG clock must be enabled in order to do register writes
108-
apb2.enr().modify(|_, w| w.syscfgen().set_bit());
108+
SYSCFG::enable(apb2);
109109

110110
let i = self.pin_id();
111111
let port = self.port_id() as u32;
@@ -232,14 +232,14 @@ impl<const P: char> PUPDR<P> {
232232
}
233233

234234
macro_rules! gpio {
235-
($GPIOX:ident, $gpiox:ident, $gpioy:ident, $iopxenr:ident, $iopxrst:ident, $PXx:ident, $port_id:literal, $extigpionr:expr, [
235+
($GPIOX:ident, $gpiox:ident, $PXx:ident, $port_id:literal, $extigpionr:expr, [
236236
$($PXi:ident: ($pxi:ident, $i:expr, $MODE:ty, $HL:ident, $exticri:ident),)+
237237
]) => {
238238
/// GPIO
239239
pub mod $gpiox {
240240
use crate::stm32::$GPIOX;
241241

242-
use crate::rcc::AHB2;
242+
use crate::rcc::{AHB2, Enable, Reset};
243243
use super::{
244244
Afr,
245245
Pin,
@@ -280,9 +280,8 @@ macro_rules! gpio {
280280
type Parts = Parts;
281281

282282
fn split(self, ahb: &mut AHB2) -> Parts {
283-
ahb.enr().modify(|_, w| w.$iopxenr().set_bit());
284-
ahb.rstr().modify(|_, w| w.$iopxrst().set_bit());
285-
ahb.rstr().modify(|_, w| w.$iopxrst().clear_bit());
283+
<$GPIOX>::enable(ahb);
284+
<$GPIOX>::reset(ahb);
286285

287286
Parts {
288287
afrh: Afr::new(),
@@ -615,7 +614,7 @@ macro_rules! af {
615614
af!(H8, AFRH, afrh);
616615
af!(L8, AFRL, afrl);
617616

618-
gpio!(GPIOA, gpioa, gpioa, gpioaen, gpioarst, PAx, 'A', 0, [
617+
gpio!(GPIOA, gpioa, PAx, 'A', 0, [
619618
PA0: (pa0, 0, Input<Floating>, L8, exticr1),
620619
PA1: (pa1, 1, Input<Floating>, L8, exticr1),
621620
PA2: (pa2, 2, Input<Floating>, L8, exticr1),
@@ -634,7 +633,7 @@ gpio!(GPIOA, gpioa, gpioa, gpioaen, gpioarst, PAx, 'A', 0, [
634633
PA15: (pa15, 15, Input<Floating>, H8, exticr4),
635634
]);
636635

637-
gpio!(GPIOB, gpiob, gpioa, gpioben, gpiobrst, PBx, 'B', 1, [
636+
gpio!(GPIOB, gpiob, PBx, 'B', 1, [
638637
PB0: (pb0, 0, Input<Floating>, L8, exticr1),
639638
PB1: (pb1, 1, Input<Floating>, L8, exticr1),
640639
PB2: (pb2, 2, Input<Floating>, L8, exticr1),
@@ -653,7 +652,7 @@ gpio!(GPIOB, gpiob, gpioa, gpioben, gpiobrst, PBx, 'B', 1, [
653652
PB15: (pb15, 15, Input<Floating>, H8, exticr4),
654653
]);
655654

656-
gpio!(GPIOC, gpioc, gpioa, gpiocen, gpiocrst, PCx, 'C', 2, [
655+
gpio!(GPIOC, gpioc, PCx, 'C', 2, [
657656
PC0: (pc0, 0, Input<Floating>, L8, exticr1),
658657
PC1: (pc1, 1, Input<Floating>, L8, exticr1),
659658
PC2: (pc2, 2, Input<Floating>, L8, exticr1),
@@ -672,7 +671,7 @@ gpio!(GPIOC, gpioc, gpioa, gpiocen, gpiocrst, PCx, 'C', 2, [
672671
PC15: (pc15, 15, Input<Floating>, H8, exticr4),
673672
]);
674673

675-
gpio!(GPIOD, gpiod, gpioa, gpioden, gpiodrst, PDx, 'D', 3, [
674+
gpio!(GPIOD, gpiod, PDx, 'D', 3, [
676675
PD0: (pd0, 0, Input<Floating>, L8, exticr1),
677676
PD1: (pd1, 1, Input<Floating>, L8, exticr1),
678677
PD2: (pd2, 2, Input<Floating>, L8, exticr1),
@@ -691,7 +690,7 @@ gpio!(GPIOD, gpiod, gpioa, gpioden, gpiodrst, PDx, 'D', 3, [
691690
PD15: (pd15, 15, Input<Floating>, H8, exticr4),
692691
]);
693692

694-
gpio!(GPIOE, gpioe, gpioa, gpioeen, gpioerst, PEx, 'E', 4, [
693+
gpio!(GPIOE, gpioe, PEx, 'E', 4, [
695694
PE0: (pe0, 0, Input<Floating>, L8, exticr1),
696695
PE1: (pe1, 1, Input<Floating>, L8, exticr1),
697696
PE2: (pe2, 2, Input<Floating>, L8, exticr1),
@@ -711,7 +710,7 @@ gpio!(GPIOE, gpioe, gpioa, gpioeen, gpioerst, PEx, 'E', 4, [
711710
]);
712711

713712
#[cfg(any(feature = "stm32l4x5", feature = "stm32l4x6"))]
714-
gpio!(GPIOF, gpiof, gpioa, gpiofen, gpiofrst, PFx, 'F', 5, [
713+
gpio!(GPIOF, gpiof, PFx, 'F', 5, [
715714
PF0: (pf0, 0, Input<Floating>, L8, exticr1),
716715
PF1: (pf1, 1, Input<Floating>, L8, exticr1),
717716
PF2: (pf2, 2, Input<Floating>, L8, exticr1),
@@ -731,7 +730,7 @@ gpio!(GPIOF, gpiof, gpioa, gpiofen, gpiofrst, PFx, 'F', 5, [
731730
]);
732731

733732
#[cfg(any(feature = "stm32l4x5", feature = "stm32l4x6"))]
734-
gpio!(GPIOG, gpiog, gpioa, gpiogen, gpiogrst, PGx, 'G', 6, [
733+
gpio!(GPIOG, gpiog, PGx, 'G', 6, [
735734
PG0: (pg0, 0, Input<Floating>, L8, exticr1),
736735
PG1: (pg1, 1, Input<Floating>, L8, exticr1),
737736
PG2: (pg2, 2, Input<Floating>, L8, exticr1),

‎src/i2c.rs

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,10 @@ use crate::hal::blocking::i2c::{Read, Write, WriteRead};
66
#[cfg(any(feature = "stm32l4x1", feature = "stm32l4x2", feature = "stm32l4x6"))]
77
use crate::pac::I2C4;
88
use crate::pac::{i2c1, I2C1, I2C2, I2C3};
9+
#[cfg(any(feature = "stm32l4x1", feature = "stm32l4x2", feature = "stm32l4x6"))]
10+
use crate::rcc::APB1R2;
911

10-
use crate::rcc::{Clocks, APB1R1};
12+
use crate::rcc::{Clocks, Enable, RccBus, Reset};
1113
use crate::time::Hertz;
1214
use cast::{u16, u8};
1315
use core::ops::Deref;
@@ -161,37 +163,36 @@ impl Config {
161163
}
162164

163165
macro_rules! hal {
164-
($i2c_type: ident, $enr: ident, $rstr: ident, $i2cX: ident, $i2cXen: ident, $i2cXrst: ident) => {
166+
($i2c_type: ident, $i2cX: ident) => {
165167
impl<SCL, SDA> I2c<$i2c_type, (SCL, SDA)> {
166168
pub fn $i2cX(
167169
i2c: $i2c_type,
168170
pins: (SCL, SDA),
169171
config: Config,
170-
apb1: &mut APB1R1,
172+
apb1: &mut <$i2c_type as RccBus>::Bus,
171173
) -> Self
172174
where
173175
SCL: SclPin<$i2c_type>,
174176
SDA: SdaPin<$i2c_type>,
175177
{
176-
apb1.$enr().modify(|_, w| w.$i2cXen().set_bit());
177-
apb1.$rstr().modify(|_, w| w.$i2cXrst().set_bit());
178-
apb1.$rstr().modify(|_, w| w.$i2cXrst().clear_bit());
178+
<$i2c_type>::enable(apb1);
179+
<$i2c_type>::reset(apb1);
179180
Self::new(i2c, pins, config)
180181
}
181182
}
182183
};
183184
}
184185

185-
hal!(I2C1, enr, rstr, i2c1, i2c1en, i2c1rst);
186-
hal!(I2C2, enr, rstr, i2c2, i2c2en, i2c2rst);
187-
hal!(I2C3, enr, rstr, i2c3, i2c3en, i2c3rst);
186+
hal!(I2C1, i2c1);
187+
hal!(I2C2, i2c2);
188+
hal!(I2C3, i2c3);
188189

189190
// This peripheral is not present on
190191
// STM32L471XX and STM32L431XX
191192
// STM32L432XX and STM32l442XX
192193
// STM32L486XX and STM32L476XX
193194
#[cfg(any(feature = "stm32l4x1", feature = "stm32l4x2", feature = "stm32l4x6"))]
194-
hal!(I2C4, enr2, rstr2, i2c4, i2c4en, i2c4rst);
195+
hal!(I2C4, i2c4);
195196

196197
impl<SCL, SDA, I2C> I2c<I2C, (SCL, SDA)>
197198
where

‎src/lptimer.rs

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//! Low power timers
2-
use crate::rcc::{Clocks, APB1R1, APB1R2, CCIPR};
2+
use crate::rcc::{Clocks, Enable, RccBus, Reset, CCIPR};
33

44
use crate::stm32::{LPTIM1, LPTIM2, RCC};
55

@@ -112,7 +112,7 @@ pub struct LowPowerTimer<LPTIM> {
112112
}
113113

114114
macro_rules! hal {
115-
($timer_type: ident, $lptimX: ident, $apb1rX: ident, $timXen: ident, $timXrst: ident, $timXsel: ident) => {
115+
($timer_type: ident, $lptimX: ident, $timXsel: ident) => {
116116
impl LowPowerTimer<$timer_type> {
117117
#[inline(always)]
118118
fn enable(&mut self) {
@@ -146,7 +146,7 @@ macro_rules! hal {
146146
pub fn $lptimX(
147147
lptim: $timer_type,
148148
config: LowPowerTimerConfig,
149-
apb1rn: &mut $apb1rX,
149+
apb1rn: &mut <$timer_type as RccBus>::Bus,
150150
ccipr: &mut CCIPR,
151151
clocks: Clocks,
152152
) -> Self {
@@ -175,9 +175,8 @@ macro_rules! hal {
175175
_ => {}
176176
}
177177

178-
apb1rn.enr().modify(|_, w| w.$timXen().set_bit());
179-
apb1rn.rstr().modify(|_, w| w.$timXrst().set_bit());
180-
apb1rn.rstr().modify(|_, w| w.$timXrst().clear_bit());
178+
<$timer_type>::enable(apb1rn);
179+
<$timer_type>::reset(apb1rn);
181180

182181
// This operation is sound as `ClockSource as u8` only produces valid values
183182
ccipr
@@ -313,5 +312,5 @@ macro_rules! hal {
313312
};
314313
}
315314

316-
hal!(LPTIM1, lptim1, APB1R1, lptim1en, lptim1rst, lptim1sel);
317-
hal!(LPTIM2, lptim2, APB1R2, lptim2en, lptim2rst, lptim2sel);
315+
hal!(LPTIM1, lptim1, lptim1sel);
316+
hal!(LPTIM2, lptim2, lptim2sel);

‎src/otg_fs.rs

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
//!
33
//! The STM32L4 series only supports the full-speed peripheral.
44
5+
use crate::rcc::{Enable, Reset};
56
use crate::stm32;
67

78
use crate::gpio::{
@@ -34,16 +35,12 @@ unsafe impl UsbPeripheral for USB {
3435
const ENDPOINT_COUNT: usize = 6;
3536

3637
fn enable() {
37-
let rcc = unsafe { &*stm32::RCC::ptr() };
38-
39-
cortex_m::interrupt::free(|_| {
38+
cortex_m::interrupt::free(|_| unsafe {
4039
// Enable USB peripheral
41-
rcc.ahb2enr.modify(|_, w| w.otgfsen().set_bit());
42-
let _ = rcc.ahb2enr.read().otgfsen().bit_is_set();
40+
stm32::OTG_FS_GLOBAL::enable_unchecked();
4341

4442
// Reset USB peripheral
45-
rcc.ahb2rstr.modify(|_, w| w.otgfsrst().set_bit());
46-
rcc.ahb2rstr.modify(|_, w| w.otgfsrst().clear_bit());
43+
stm32::OTG_FS_GLOBAL::reset_unchecked();
4744
});
4845
}
4946

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