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Use new dmamux interface in adc.rs, serial.rs and spi.rs
1 parent 8bad0e8 commit 70f465b

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3 files changed

+22
-25
lines changed

3 files changed

+22
-25
lines changed

‎src/adc.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ use core::{
88

99
use crate::{
1010
dma::{dma1, Event as DMAEvent, RxDma, Transfer, TransferPayload, W},
11+
dmamux::{DmaInput, DmaMux},
1112
gpio::{self, Analog},
1213
hal::{
1314
adc::{Channel as EmbeddedHalChannel, OneShot},
@@ -526,7 +527,7 @@ where
526527
channel.set_memory_address(buffer.as_ptr() as u32, true);
527528
channel.set_transfer_length(N as u16);
528529

529-
channel.cselr().modify(|_, w| w.c1s().bits(0b0000));
530+
channel.set_request_line(DmaInput::Adc1).unwrap();
530531

531532
channel.ccr().modify(|_, w| unsafe {
532533
w.mem2mem()

‎src/serial.rs

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ use crate::dma::{
1616
dma1, CircBuffer, DMAFrame, FrameReader, FrameSender, Receive, RxDma, TransferPayload,
1717
Transmit, TxDma,
1818
};
19+
use crate::dmamux::{DmaInput, DmaMux};
1920
use crate::gpio::{self, Alternate, OpenDrain, PushPull};
2021
use crate::pac;
2122
use crate::rcc::{Clocks, Enable, RccBus, Reset};
@@ -225,8 +226,8 @@ macro_rules! hal {
225226
$USARTX:ident: (
226227
$usartX:ident,
227228
$pclkX:ident,
228-
tx: ($txdma:ident, $dmacst:ident, $dmatxch:path),
229-
rx: ($rxdma:ident, $dmacsr:ident, $dmarxch:path)
229+
tx: ($txdma:ident, $dmatxch:path, $dmatxsel:path),
230+
rx: ($rxdma:ident, $dmarxch:path, $dmarxsel:path)
230231
),
231232
)+) => {
232233
$(
@@ -721,9 +722,7 @@ macro_rules! hal {
721722
self.channel.set_transfer_length(len as u16);
722723

723724
// Tell DMA to request from serial
724-
self.channel.cselr().modify(|_, w| {
725-
w.$dmacsr().map2()
726-
});
725+
self.channel.set_request_line($dmarxsel).unwrap();
727726

728727
self.channel.ccr().modify(|_, w| {
729728
w
@@ -776,9 +775,7 @@ macro_rules! hal {
776775
self.channel.set_transfer_length(buf.max_len() as u16);
777776

778777
// Tell DMA to request from serial
779-
self.channel.cselr().modify(|_, w| {
780-
w.$dmacsr().map2()
781-
});
778+
self.channel.set_request_line($dmarxsel).unwrap();
782779

783780
self.channel.ccr().modify(|_, w| {
784781
w
@@ -823,9 +820,7 @@ macro_rules! hal {
823820
self.channel.set_peripheral_address(&usart.tdr as *const _ as u32, false);
824821

825822
// Tell DMA to request from serial
826-
self.channel.cselr().modify(|_, w| {
827-
w.$dmacst().map2()
828-
});
823+
self.channel.set_request_line($dmatxsel).unwrap();
829824

830825
self.channel.ccr().modify(|_, w| unsafe {
831826
w.mem2mem()
@@ -852,13 +847,13 @@ macro_rules! hal {
852847
}
853848

854849
hal! {
855-
USART1: (usart1, pclk2, tx: (TxDma1, c4s, dma1::C4), rx: (RxDma1, c5s, dma1::C5)),
856-
USART2: (usart2, pclk1, tx: (TxDma2, c7s, dma1::C7), rx: (RxDma2, c6s, dma1::C6)),
850+
USART1: (usart1, pclk2, tx: (TxDma1, dma1::C4, DmaInput::Usart1Tx), rx: (RxDma1, dma1::C5, DmaInput::Usart1Rx)),
851+
USART2: (usart2, pclk1, tx: (TxDma2, dma1::C7, DmaInput::Usart2Tx), rx: (RxDma2, dma1::C6, DmaInput::Usart2Rx)),
857852
}
858853

859854
#[cfg(not(any(feature = "stm32l432", feature = "stm32l442")))]
860855
hal! {
861-
USART3: (usart3, pclk1, tx: (TxDma3, c2s, dma1::C2), rx: (RxDma3, c3s, dma1::C3)),
856+
USART3: (usart3, pclk1, tx: (TxDma3, dma1::C2, DmaInput::Usart3Tx), rx: (RxDma3, dma1::C3, DmaInput::Usart3Rx)),
862857
}
863858

864859
#[cfg(any(
@@ -882,7 +877,7 @@ hal! {
882877
feature = "stm32l4s9",
883878
))]
884879
hal! {
885-
UART4: (uart4, pclk1, tx: (TxDma4, c3s, dma2::C3), rx: (RxDma4, c5s, dma2::C5)),
880+
UART4: (uart4, pclk1, tx: (TxDma4, dma2::C3, DmaInput::Uart4Tx), rx: (RxDma4, dma2::C5, DmaInput::Uart4Rx)),
886881
}
887882

888883
#[cfg(any(
@@ -903,7 +898,7 @@ hal! {
903898
feature = "stm32l4s9",
904899
))]
905900
hal! {
906-
UART5: (uart5, pclk1, tx: (TxDma5, c1s, dma2::C1), rx: (RxDma5, c2s, dma2::C2)),
901+
UART5: (uart5, pclk1, tx: (TxDma5, dma2::C1, DmaInput::Uart5Tx), rx: (RxDma5, dma2::C2, DmaInput::Uart5Rx)),
907902
}
908903

909904
impl<USART, PINS> fmt::Write for Serial<USART, PINS>

‎src/spi.rs

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ use core::sync::atomic::Ordering;
1212
#[cfg(not(any(feature = "stm32l433", feature = "stm32l443",)))]
1313
use crate::dma::dma2;
1414
use crate::dma::{self, dma1, TransferPayload};
15+
use crate::dmamux::{DmaInput, DmaMux};
1516
use crate::gpio::{Alternate, PushPull};
1617
use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
1718
use crate::rcc::{Clocks, Enable, RccBus, Reset};
@@ -370,7 +371,7 @@ pub type SpiTxDma<SPI, PINS, CHANNEL> = dma::TxDma<SpiPayload<SPI, PINS>, CHANNE
370371
pub type SpiRxTxDma<SPI, PINS, RXCH, TXCH> = dma::RxTxDma<SpiPayload<SPI, PINS>, RXCH, TXCH>;
371372

372373
macro_rules! spi_dma {
373-
($SPIX:ident, $RX_CH:path, $RX_CHX:ident, $RX_MAPX:ident, $TX_CH:path, $TX_CHX:ident, $TX_MAPX:ident) => {
374+
($SPIX:ident, $RX_CH:path, $RX_CHSEL:path, $TX_CH:path, $TX_CHSEL:path) => {
374375
impl<PINS> dma::Receive for SpiRxDma<$SPIX, PINS, $RX_CH> {
375376
type RxChannel = $RX_CH;
376377
type TransmittedWord = u8;
@@ -397,7 +398,7 @@ macro_rules! spi_dma {
397398
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
398399
false,
399400
);
400-
channel.cselr().modify(|_, w| w.$RX_CHX().$RX_MAPX());
401+
channel.set_request_line($RX_CHSEL).unwrap();
401402
channel.ccr().modify(|_, w| {
402403
w
403404
// memory to memory mode disabled
@@ -432,7 +433,7 @@ macro_rules! spi_dma {
432433
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
433434
false,
434435
);
435-
channel.cselr().modify(|_, w| w.$TX_CHX().$TX_MAPX());
436+
channel.set_request_line($TX_CHSEL).unwrap();
436437
channel.ccr().modify(|_, w| {
437438
w
438439
// memory to memory mode disabled
@@ -474,7 +475,7 @@ macro_rules! spi_dma {
474475
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
475476
false,
476477
);
477-
rx_channel.cselr().modify(|_, w| w.$RX_CHX().$RX_MAPX());
478+
rx_channel.set_request_line($RX_CHSEL).unwrap();
478479

479480
rx_channel.ccr().modify(|_, w| {
480481
w
@@ -505,7 +506,7 @@ macro_rules! spi_dma {
505506
unsafe { &(*$SPIX::ptr()).dr as *const _ as u32 },
506507
false,
507508
);
508-
tx_channel.cselr().modify(|_, w| w.$TX_CHX().$TX_MAPX());
509+
tx_channel.set_request_line($TX_CHSEL).unwrap();
509510

510511
tx_channel.ccr().modify(|_, w| {
511512
w
@@ -765,7 +766,7 @@ macro_rules! spi_dma {
765766
};
766767
}
767768

768-
spi_dma!(SPI1, dma1::C2, c2s, map1, dma1::C3, c3s, map1);
769+
spi_dma!(SPI1, dma1::C2, DmaInput::Spi1Rx, dma1::C3, DmaInput::Spi1Tx);
769770
#[cfg(not(any(
770771
feature = "stm32l412",
771772
feature = "stm32l422",
@@ -774,7 +775,7 @@ spi_dma!(SPI1, dma1::C2, c2s, map1, dma1::C3, c3s, map1);
774775
feature = "stm32l452",
775776
feature = "stm32l462",
776777
)))]
777-
spi_dma!(SPI2, dma1::C4, c4s, map1, dma1::C5, c5s, map1);
778+
spi_dma!(SPI2, dma1::C4, DmaInput::Spi2Rx, dma1::C5, DmaInput::Spi2Tx);
778779
// spi_dma!(SPI1, dma2::C3, c3s, map4, dma2::C4, c4s, map4);
779780
#[cfg(not(any(feature = "stm32l433", feature = "stm32l443",)))]
780-
spi_dma!(SPI3, dma2::C1, c1s, map3, dma2::C2, c2s, map3);
781+
spi_dma!(SPI3, dma2::C1, DmaInput::Spi3Rx, dma2::C2, DmaInput::Spi3Tx);

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