Fix clock assertion.

reitermarkus · web-flow · commit 6c861b466c36 · 2022-05-26T19:27:12.000+02:00
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -754,7 +754,7 @@ impl CFGR {
             pll48m1clk = Some((vco / q).Hz());
 
             if self.clk48_source == Some(Clk48Source::Pll) {
-                assert_eq!(q, 48_000_000);
+                assert_eq!(pll48m1clk, 48_000_000);
             }
 
             assert!(r <= 8); // Allowed max output divider

Original file line number	Diff line number	Diff line change
`@@ -754,7 +754,7 @@ impl CFGR {`
`754`	`754`	`pll48m1clk = Some((vco / q).Hz());`
`755`	`755`
`756`	`756`	`if self.clk48_source == Some(Clk48Source::Pll) {`
`757`		`- assert_eq!(q, 48_000_000);`
	`757`	`+ assert_eq!(pll48m1clk, 48_000_000);`
`758`	`758`	`}`
`759`	`759`
`760`	`760`	`assert!(r <= 8); // Allowed max output divider`