Merge branch 'master' into stm32l4r5

Author: gauteh

.github/workflows/ci.yml

@@ -51,3 +51,34 @@ jobs:
         with:
           command: test
           args: --lib --target x86_64-unknown-linux-gnu --features rt,unproven,${{ matrix.mcu }}
+
+  ci-r9:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+        mcu:
+          - stm32l4r9
+          - stm32l4s9
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: ${{ matrix.rust }}
+          target: thumbv7em-none-eabihf
+          override: true
+      - name: build
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: build
+          args: --verbose --release --target thumbv7em-none-eabihf --features rt,unproven,${{ matrix.mcu }}
+      # note that examples were not built
+      - name: test
+        uses: actions-rs/cargo@v1
+        with:
+          command: test
+          args: --lib --target x86_64-unknown-linux-gnu --features rt,unproven,${{ matrix.mcu }}

CHANGELOG.md

@@ -7,6 +7,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ## Changed
 
+    - Use `fugit` duration nd rate units instead of custom
     - Use const-generics for GPIO (require Rust 1.51)
 
 ## [v0.6.0] - 2020-12-11

Cargo.toml

@@ -26,6 +26,7 @@ nb = "0.1.1"
 stm32l4 = "0.14.0"
 embedded-dma = "0.1"
 bxcan = ">=0.4, <0.7"
+fugit = "0.3.5"
 
 [dependencies.rand_core]
 version = "0.6.2"

examples/adc_dma.rs

@@ -8,7 +8,6 @@ use stm32l4xx_hal::{
     delay::DelayCM,
     dma::{dma1, RxDma, Transfer, W},
     prelude::*,
-    time::Hertz,
 };
 
 use rtic::app;
@@ -51,10 +50,7 @@ const APP: () = {
         //
         // Initialize the clocks
         //
-        let clocks = rcc
-            .cfgr
-            .sysclk(Hertz(80_000_000))
-            .freeze(&mut flash.acr, &mut pwr);
+        let clocks = rcc.cfgr.sysclk(80.MHz()).freeze(&mut flash.acr, &mut pwr);
 
         let mut delay = DelayCM::new(clocks);
 

examples/blinky.rs

@@ -34,10 +34,10 @@ fn main() -> ! {
     let mut pwr = dp.PWR.constrain(&mut rcc.apb1r1);
 
     // Try a different clock configuration
-    let clocks = rcc.cfgr.hclk(8.mhz()).freeze(&mut flash.acr, &mut pwr);
+    let clocks = rcc.cfgr.hclk(8.MHz()).freeze(&mut flash.acr, &mut pwr);
     // let clocks = rcc.cfgr
-    //     .sysclk(64.mhz())
-    //     .pclk1(32.mhz())
+    //     .sysclk(64.MHz())
+    //     .pclk1(32.MHz())
     //     .freeze(&mut flash.acr);
 
     // let mut gpioc = dp.GPIOC.split(&mut rcc.ahb2);

examples/can-loopback.rs

@@ -28,7 +28,7 @@ const APP: () = {
         let mut gpioa = dp.GPIOA.split(&mut rcc.ahb2);
 
         // Set the clocks to 80 MHz
-        let _clocks = rcc.cfgr.sysclk(80.mhz()).freeze(&mut flash.acr, &mut pwr);
+        let _clocks = rcc.cfgr.sysclk(80.MHz()).freeze(&mut flash.acr, &mut pwr);
 
         rprintln!("  - CAN init");
 

examples/i2c_write.rs

@@ -52,7 +52,7 @@ fn main() -> ! {
     let mut i2c = I2c::i2c1(
         dp.I2C1,
         (scl, sda),
-        i2c::Config::new(100.khz(), clocks),
+        i2c::Config::new(100.kHz(), clocks),
         &mut rcc.apb1r1,
     );
 

examples/irq_button.rs

@@ -33,10 +33,10 @@ fn main() -> ! {
         let mut pwr = dp.PWR.constrain(&mut rcc.apb1r1);
 
         rcc.cfgr
-            .hclk(48.mhz())
-            .sysclk(80.mhz())
-            .pclk1(24.mhz())
-            .pclk2(24.mhz())
+            .hclk(48.MHz())
+            .sysclk(80.MHz())
+            .pclk1(24.MHz())
+            .pclk2(24.MHz())
             .freeze(&mut flash.acr, &mut pwr);
 
         // Create a button input with an interrupt

examples/lptim_rtic.rs

@@ -15,7 +15,6 @@ use stm32l4xx_hal::{
     prelude::*,
     pwr::Pwr,
     rcc::{ClockSecuritySystem, Clocks, CrystalBypass, RccExt, CFGR},
-    time::U32Ext,
 };
 
 // this is the LD4 on Nucleo-L452-P
@@ -24,7 +23,7 @@ type Timer = LowPowerTimer<LPTIM1>;
 
 pub fn configure_clock_tree(cfgr: CFGR, acr: &mut ACR, pwr: &mut Pwr) -> Clocks {
     cfgr.lse(CrystalBypass::Disable, ClockSecuritySystem::Disable)
-        .sysclk(80.mhz())
+        .sysclk(80.MHz())
         .freeze(acr, pwr)
 }
 

examples/otg_fs_serial.rs

@@ -111,22 +111,22 @@ unsafe fn main() -> ! {
             rcc.cfgr
                 .msi(MsiFreq::RANGE48M) // Set the MSI (multi-speed internal) clock to 48 MHz
                 .pll_source(PllSource::MSI)
-                .sysclk_with_pll(80.mhz(), pll_cfg)
-                .pclk1(24.mhz())
-                .pclk2(24.mhz())
+                .sysclk_with_pll(80.MHz(), pll_cfg)
+                .pclk1(24.MHz())
+                .pclk2(24.MHz())
                 .freeze(&mut flash.acr, &mut pwr)
         } else {
             // Note: If program needs low-speed clocks, adjust this.
             //       Tested using a 16 MHz resonator.
             rcc.cfgr
                 .msi(MsiFreq::RANGE48M)
                 .hse(
-                    16.mhz(),
+                    16.MHz(),
                     CrystalBypass::Disable, // Bypass enabled when clock signals instead of crystals/resonators are used.
                     ClockSecuritySystem::Disable, // We have not set up interrupt routines handling clock drifts/errors.
                 )
                 .pll_source(PllSource::HSE)
-                .sysclk(80.mhz())
+                .sysclk(80.MHz())
                 .freeze(&mut flash.acr, &mut pwr)
         }
     };