Skip to content

Commit a0522fc

Browse files
committed
Set the Update Generation bit in order to reset counters, in particular the prescaler's, before starting the timer. Since it is set when Update Reset Source is set high no interrupt will be generated.
1 parent 469a51a commit a0522fc

File tree

1 file changed

+4
-0
lines changed

1 file changed

+4
-0
lines changed

src/timer.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,11 @@ macro_rules! timers {
172172
}
173173
);
174174

175+
// Load prescaler value and reset its counter.
176+
// Setting URS makes sure no interrupt is generated.
175177
self.tim.cr1.modify(|_, w| w.urs().set_bit());
178+
self.tim.egr.write(|w| w.ug().set_bit());
179+
176180
self.tim.cr1.modify(|_, w| w.cen().set_bit());
177181
}
178182

0 commit comments

Comments
 (0)