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Add support for low-power run mode
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src/pwr.rs

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@@ -11,6 +11,7 @@ use cortex_m::{
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use crate::{
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pac,
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rcc::{
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Clocks,
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ClockSrc,
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PLLSource,
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Rcc,
@@ -67,6 +68,47 @@ impl PWR {
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VcoreRange::from_bits(vos)
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}
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/// Enters low-power run mode
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///
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/// Please note that there are some restrictions placed on low-power run
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/// mode. Please refer to the STM32L0x2 reference manual, section 6.3.4 for
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/// more information.
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///
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/// # Panics
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///
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/// To enter low-power run mode, the system clock frequency should not
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/// exceed the MSI frequency range 1 (131.072 kHz). This method will panic,
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/// if that is the case.
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pub fn enter_low_power_run_mode(&mut self, clocks: Clocks) {
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// This follows the procedure laid out in the STM32L0x2 reference
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// manual, section 6.3.4.
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// Panic, if system clock frequency is outside of allowed range. See
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// STM32L0x1/STM32L0x2/STM32L0x3 reference manuals, sections 6.3.4 and
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// 7.2.3.
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assert!(clocks.sys_clk().0 <= 131_072);
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self.switch_vcore_range(VcoreRange::Range2);
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// First set LPSDSR, then LPRUN, to go into low-power run mode. See
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// STM32L0x2 reference manual, section 6.4.1.
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self.set_lpsdsr();
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self.0.cr.modify(|_, w| w.lprun().set_bit());
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}
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/// Exit low-power run mode
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///
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/// Please note that entering low-power run mode sets Vcore to range 2. This
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/// method will not switch Vcore again, so please make sure to restore the
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/// previous Vcore setting again, if you want to do so. See
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/// [`PWR::switch_vcore_range`]/[`PRW::get_vcore_range`] for more info.
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pub fn exit_low_power_run_mode(&mut self) {
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// First reset LPRUN, then LPSDSR. See STM32L0x2 reference manual,
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// section 6.4.1.
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self.0.cr.modify(|_, w| w.lprun().clear_bit());
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self.clear_lpsdsr();
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}
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/// Returns a struct that can be used to enter Sleep mode
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pub fn sleep_mode<'r>(&'r mut self, scb: &'r mut SCB) -> SleepMode<'r> {
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SleepMode {

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