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Merge pull request #65 from craigjb/master
Fix PLL enable.
2 parents dd1cebb + 317f8c6 commit 68eeba6

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+11
-19
lines changed

1 file changed

+11
-19
lines changed

src/rcc.rs

Lines changed: 11 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,9 @@ use crate::time::{Hertz, U32Ext};
44
#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
55
use crate::{
66
pac::CRS,
7-
syscfg::SYSCFG,
7+
syscfg::SYSCFG
88
};
99

10-
1110
/// System clock mux source
1211
#[derive(Clone, Copy)]
1312
pub enum ClockSrc {
@@ -199,27 +198,22 @@ impl Rcc {
199198
// Initialize CRS
200199
crs.cfgr.write(|w|
201200
// Select LSE as synchronization source
202-
unsafe { w.syncsrc().bits(0b01) }
203-
);
204-
crs.cr.write(|w|
205-
w
206-
.autotrimen().set_bit()
207-
.cen().set_bit()
208-
);
201+
unsafe { w.syncsrc().bits(0b01) });
202+
crs.cr
203+
.modify(|_, w| w.autotrimen().set_bit().cen().set_bit());
209204

210205
// Enable VREFINT reference for HSI48 oscillator
211-
syscfg.syscfg.cfgr3.modify(|_, w|
212-
w
213-
.enref_hsi48().set_bit()
214-
.en_vrefint().set_bit()
215-
);
206+
syscfg
207+
.syscfg
208+
.cfgr3
209+
.modify(|_, w| w.enref_hsi48().set_bit().en_vrefint().set_bit());
216210

217211
// Select HSI48 as USB clock
218212
self.rb.ccipr.modify(|_, w| w.hsi48msel().set_bit());
219213

220214
// Enable dedicated USB clock
221215
self.rb.crrcr.modify(|_, w| w.hsi48on().set_bit());
222-
while self.rb.crrcr.read().hsi48rdy().bit_is_clear() {};
216+
while self.rb.crrcr.read().hsi48rdy().bit_is_clear() {}
223217

224218
HSI48(())
225219
}
@@ -280,7 +274,7 @@ impl RccExt for RCC {
280274
};
281275

282276
// Disable PLL
283-
self.cr.write(|w| w.pllon().clear_bit());
277+
self.cr.modify(|_, w| w.pllon().clear_bit());
284278
while self.cr.read().pllrdy().bit_is_set() {}
285279

286280
let mul_bytes = mul as u8;
@@ -315,7 +309,7 @@ impl RccExt for RCC {
315309
});
316310

317311
// Enable PLL
318-
self.cr.write(|w| w.pllon().set_bit());
312+
self.cr.modify(|_, w| w.pllon().set_bit());
319313
while self.cr.read().pllrdy().bit_is_clear() {}
320314

321315
(freq, 3)
@@ -366,7 +360,6 @@ impl RccExt for RCC {
366360

367361
Rcc { rb: self, clocks }
368362
}
369-
370363
}
371364

372365
/// Frozen clock frequencies
@@ -420,7 +413,6 @@ impl Clocks {
420413
}
421414
}
422415

423-
424416
/// Token that exists only, if the HSI48 clock has been enabled
425417
///
426418
/// You can get an instance of this struct by calling [`Rcc::enable_hsi48`].

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