Update to new stm32l0 release

jonas-schievink · jonas-schievink · commit 519d72949792 · 2019-11-13T13:15:23.000+01:00
diff --git a/Cargo.toml b/Cargo.toml
@@ -27,6 +27,7 @@ version = "0.4.0"
 features = ["stm32l0x1", "rt"]
 
 [dependencies]
+stm32l0 = "0.9.0"
 as-slice = "0.1.0"
 embedded-hal = { version = "0.2.3", features = ["unproven"] }
 cortex-m = {version = "0.6.1", features = ["const-fn"] }
@@ -36,9 +37,6 @@ void = { version = "1.0.2", default-features = false }
 cast = { version = "0.2.2", default-features = false }
 nb = "0.1.2"
 
-[dependencies.stm32l0]
-version = "0.8.0"
-
 [dev-dependencies]
 aligned = "0.3.1"
 heapless = "0.5.0"
diff --git a/src/adc.rs b/src/adc.rs
@@ -110,22 +110,12 @@ impl Adc {
         while self.rb.cr.read().aden().bit_is_set() {}
     }
 
-    #[cfg(feature = "stm32l0x1")]
     fn write_smpr(&mut self) {
         self.rb
             .smpr
             .modify(|_, w| w.smp().bits(self.sample_time as u8));
     }
 
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    fn write_smpr(&mut self) {
-        self.rb
-            .smpr
-            // Safe, because `self.sample_time` is of type `SampleTime`, which
-            // defines only valid values.
-            .modify(|_, w| unsafe { w.smpr().bits(self.sample_time as u8) });
-    }
-
     pub fn release(self) -> ADC {
         self.rb
     }
@@ -156,8 +146,7 @@ where
             //
             // The `bits` method is not unsafe on STM32L0x1, so we need to
             // suppress the warning there.
-            #[cfg_attr(feature = "stm32l0x1", allow(unused_unsafe))]
-            let w = unsafe { w.res().bits(self.precision as u8) };
+            let w = w.res().bits(self.precision as u8);
             w.align().bit(self.align == Align::Left)
         });
 
diff --git a/src/dma.rs b/src/dma.rs
@@ -30,7 +30,7 @@ use crate::{
     i2c,
     pac::{
         self,
-        dma1::ccr1,
+        dma1::ch::cr,
         I2C1,
         I2C2,
         I2C3,
@@ -222,37 +222,37 @@ impl<T, C, B> fmt::Debug for TransferResources<T, C, B> {
 
 
 /// The priority of the DMA transfer
-pub struct Priority(ccr1::PLW);
+pub struct Priority(cr::PL_A);
 
 impl Priority {
     pub fn low() -> Self {
-        Self(ccr1::PLW::LOW)
+        Self(cr::PL_A::LOW)
     }
 
     pub fn medium() -> Self {
-        Self(ccr1::PLW::MEDIUM)
+        Self(cr::PL_A::MEDIUM)
     }
 
     pub fn high() -> Self {
-        Self(ccr1::PLW::HIGH)
+        Self(cr::PL_A::HIGH)
     }
 
     pub fn very_high() -> Self {
-        Self(ccr1::PLW::VERYHIGH)
+        Self(cr::PL_A::VERYHIGH)
     }
 }
 
 
 /// The direction of the DMA transfer
-pub(crate) struct Direction(ccr1::DIRW);
+pub(crate) struct Direction(cr::DIR_A);
 
 impl Direction {
     pub fn memory_to_peripheral() -> Self {
-        Self(ccr1::DIRW::FROMMEMORY)
+        Self(cr::DIR_A::FROMMEMORY)
     }
 
     pub fn peripheral_to_memory() -> Self {
-        Self(ccr1::DIRW::FROMPERIPHERAL)
+        Self(cr::DIR_A::FROMPERIPHERAL)
     }
 }
 
@@ -268,8 +268,8 @@ pub trait Channel: Sized {
     fn set_transfer_len(&self, _: &mut Handle, len: u16);
     fn configure<Word>(&self,
         _:        &mut Handle,
-        priority: ccr1::PLW,
-        dir:      ccr1::DIRW,
+        priority: cr::PL_A,
+        dir:      cr::DIR_A,
     )
         where Word: SupportedWordSize;
     fn enable_interrupts(&self, interrupts: Interrupts);
@@ -284,11 +284,8 @@ macro_rules! impl_channel {
         $(
             $channel:ident,
             $field:ident,
+            $chfield:ident,
             $cxs:ident,
-            $cpar:ident,
-            $cmar:ident,
-            $cndtr:ident,
-            $ccr:ident,
             $tcif:ident,
             $teif:ident,
             $ctcif:ident,
@@ -322,51 +319,51 @@ macro_rules! impl_channel {
                     handle:  &mut Handle,
                     address: u32,
                 ) {
-                    handle.dma.$cpar.write(|w| w.pa().bits(address));
+                    handle.dma.$chfield.par.write(|w| w.pa().bits(address));
                 }
 
                 fn set_memory_address(&self,
                     handle:  &mut Handle,
                     address: u32,
                 ) {
-                    handle.dma.$cmar.write(|w| w.ma().bits(address));
+                    handle.dma.$chfield.mar.write(|w| w.ma().bits(address));
                 }
 
                 fn set_transfer_len(&self, handle: &mut Handle, len: u16) {
-                    handle.dma.$cndtr.write(|w| w.ndt().bits(len));
+                    handle.dma.$chfield.ndtr.write(|w| w.ndt().bits(len));
                 }
 
                 fn configure<Word>(&self,
                     handle:   &mut Handle,
-                    priority: ccr1::PLW,
-                    dir:      ccr1::DIRW,
+                    priority: cr::PL_A,
+                    dir:      cr::DIR_A,
                 )
                     where Word: SupportedWordSize
                 {
-                    handle.dma.$ccr.write(|w| {
+                    handle.dma.$chfield.cr.write(|w| {
                         // Safe, as the enum we use should only provide valid
                         // bit patterns.
                         let w = unsafe {
                             w
                                 // Word size in memory
-                                .msize().bits(Word::size()._bits())
+                                .msize().variant(Word::size())
                                 // Word size in peripheral
-                                .psize().bits(Word::size()._bits())
+                                .psize().variant(Word::size())
                         };
 
                         w
                             // Memory-to-memory mode disabled
                             .mem2mem().disabled()
                             // Priority level
-                            .pl().bits(priority._bits())
+                            .pl().variant(priority)
                             // Increment memory pointer
                             .minc().enabled()
                             // Don't increment peripheral pointer
                             .pinc().disabled()
                             // Circular mode disabled
                             .circ().disabled()
                             // Data transfer direction
-                            .dir().bit(dir._bits())
+                            .dir().variant(dir)
                             // Disable interrupts
                             .teie().disabled()
                             .htie().disabled()
@@ -377,7 +374,7 @@ macro_rules! impl_channel {
                 fn enable_interrupts(&self, interrupts: Interrupts) {
                     // Safe, because we're only accessing a register that this
                     // channel has exclusive access to.
-                    let ccr = &unsafe { &*pac::DMA1::ptr() }.$ccr;
+                    let ccr = &unsafe { &*pac::DMA1::ptr() }.$chfield.cr;
 
                     ccr.modify(|_, w|
                         w
@@ -390,7 +387,7 @@ macro_rules! impl_channel {
                 fn start(&self) {
                     // Safe, because we're only accessing a register that this
                     // channel has exclusive access to.
-                    let ccr = &unsafe { &*pac::DMA1::ptr() }.$ccr;
+                    let ccr = &unsafe { &*pac::DMA1::ptr() }.$chfield.cr;
 
                     // Start transfer
                     ccr.modify(|_, w| w.en().enabled());
@@ -419,7 +416,7 @@ macro_rules! impl_channel {
 
                     if dma.isr.read().$tcif().is_complete() {
                         dma.ifcr.write(|w| w.$ctcif().set_bit());
-                        dma.$ccr.modify(|_, w| w.en().disabled());
+                        dma.$chfield.cr.modify(|_, w| w.en().disabled());
                     }
                 }
 
@@ -444,27 +441,20 @@ macro_rules! impl_channel {
 }
 
 impl_channel!(
-    Channel1, channel1,
-        c1s, cpar1, cmar1, cndtr1, ccr1,
-        tcif1, teif1, ctcif1, cteif1;
-    Channel2, channel2,
-        c2s, cpar2, cmar2, cndtr2, ccr2,
-        tcif2, teif2, ctcif2, cteif2;
-    Channel3, channel3,
-        c3s, cpar3, cmar3, cndtr3, ccr3,
-        tcif3, teif3, ctcif3, cteif3;
-    Channel4, channel4,
-        c4s, cpar4, cmar4, cndtr4, ccr4,
-        tcif4, teif4, ctcif4, cteif4;
-    Channel5, channel5,
-        c5s, cpar5, cmar5, cndtr5, ccr5,
-        tcif5, teif5, ctcif5, cteif5;
-    Channel6, channel6,
-        c6s, cpar6, cmar6, cndtr6, ccr6,
-        tcif6, teif6, ctcif6, cteif6;
-    Channel7, channel7,
-        c7s, cpar7, cmar7, cndtr7, ccr7,
-        tcif7, teif7, ctcif7, cteif7;
+    Channel1, channel1, ch1,
+        c1s, tcif1, teif1, ctcif1, cteif1;
+    Channel2, channel2, ch2,
+        c2s, tcif2, teif2, ctcif2, cteif2;
+    Channel3, channel3, ch3,
+        c3s, tcif3, teif3, ctcif3, cteif3;
+    Channel4, channel4, ch4,
+        c4s, tcif4, teif4, ctcif4, cteif4;
+    Channel5, channel5, ch5,
+        c5s, tcif5, teif5, ctcif5, cteif5;
+    Channel6, channel6, ch6,
+        c6s, tcif6, teif6, ctcif6, cteif6;
+    Channel7, channel7, ch7,
+        c7s, tcif7, teif7, ctcif7, cteif7;
 );
 
 
@@ -580,24 +570,24 @@ impl<Word> Buffer<Word> for PtrBuffer<Word> {
 
 
 pub trait SupportedWordSize {
-    fn size() -> ccr1::MSIZEW;
+    fn size() -> cr::MSIZE_A;
 }
 
 impl SupportedWordSize for u8 {
-    fn size() -> ccr1::MSIZEW {
-        ccr1::MSIZEW::BITS8
+    fn size() -> cr::MSIZE_A {
+        cr::MSIZE_A::BITS8
     }
 }
 
 impl SupportedWordSize for u16 {
-    fn size() -> ccr1::MSIZEW {
-        ccr1::MSIZEW::BITS16
+    fn size() -> cr::MSIZE_A {
+        cr::MSIZE_A::BITS16
     }
 }
 
 impl SupportedWordSize for u32 {
-    fn size() -> ccr1::MSIZEW {
-        ccr1::MSIZEW::BITS32
+    fn size() -> cr::MSIZE_A {
+        cr::MSIZE_A::BITS32
     }
 }
 
diff --git a/src/i2c.rs b/src/i2c.rs
@@ -28,7 +28,7 @@ use crate::gpio::{AltMode, OpenDrain, Output};
 use crate::pac::{
     i2c1::{
         RegisterBlock,
-        cr2::RD_WRNW,
+        cr2::RD_WRN_A,
     }
 };
 pub use crate::pac::I2C1;
@@ -162,7 +162,7 @@ where
         (self.i2c, self.sda, self.scl)
     }
 
-    fn start_transfer(&mut self, addr: u8, len: usize, direction: RD_WRNW) {
+    fn start_transfer(&mut self, addr: u8, len: usize, direction: RD_WRN_A) {
         self.i2c.cr2.write(|w|
             w
                 // Start transfer
@@ -243,7 +243,7 @@ where
             Buffer::Target: AsSlice<Element=u8>,
     {
         assert!(buffer.len() >= num_words);
-        self.start_transfer(address, buffer.as_slice().len(), RD_WRNW::WRITE);
+        self.start_transfer(address, buffer.as_slice().len(), RD_WRN_A::WRITE);
 
         // This token represents the transmission capability of I2C and this is
         // what the `dma::Target` trait is implemented for. It can't be
@@ -316,7 +316,7 @@ where
             Buffer::Target: AsMutSlice<Element=u8>,
     {
         assert!(buffer.len() >= num_words);
-        self.start_transfer(address, buffer.as_slice().len(), RD_WRNW::READ);
+        self.start_transfer(address, buffer.as_slice().len(), RD_WRN_A::READ);
 
         // See explanation of tokens in `write_all`.
         let token = Rx(PhantomData);
@@ -370,7 +370,7 @@ where
     fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
         while self.i2c.isr.read().busy().is_busy() {}
 
-        self.start_transfer(addr, bytes.len(), RD_WRNW::WRITE);
+        self.start_transfer(addr, bytes.len(), RD_WRN_A::WRITE);
 
         // Send bytes
         for c in bytes {
@@ -390,7 +390,7 @@ where
     fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
         while self.i2c.isr.read().busy().is_busy() {}
 
-        self.start_transfer(addr, buffer.len(), RD_WRNW::READ);
+        self.start_transfer(addr, buffer.len(), RD_WRN_A::READ);
 
         // Receive bytes into buffer
         for c in buffer {
diff --git a/src/lib.rs b/src/lib.rs
@@ -24,7 +24,6 @@ pub mod adc;
 #[cfg(any(feature = "stm32l062", feature = "stm32l082"))]
 pub mod aes;
 pub mod delay;
-#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
 pub mod dma;
 pub mod exti;
 pub mod gpio;
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -230,7 +230,7 @@ impl RccExt for RCC {
                 #[cfg(feature = "stm32l0x1")]
                 self.icscr.write(|w| w.msirange().bits(range));
                 #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-                self.icscr.write(|w| unsafe { w.msirange().bits(range) });
+                self.icscr.write(|w| w.msirange().bits(range));
 
                 // Enable MSI
                 self.cr.write(|w| w.msion().set_bit());
diff --git a/src/rtc.rs b/src/rtc.rs
diff --git a/src/syscfg.rs b/src/syscfg.rs
