Add RNG driver and example

Author: lthiery

Cargo.toml

@@ -114,6 +114,10 @@ required-features = ["rt"]
 name = "i2c_dma"
 required-features = ["rt","stm32l0x2"]
 
+[[example]]
+name = "rng"
+required-features = ["rt","stm32l0x2"]
+
 [[example]]
 name = "rtc"
 required-features = ["stm32l0x2"]

examples/rng.rs

@@ -0,0 +1,34 @@
+#![no_main]
+#![no_std]
+
+
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+use stm32l0xx_hal::{pac, prelude::*, rcc::Config, syscfg::SYSCFG};
+
+use stm32l0xx_hal::rng::Rng;
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+
+    let mut rcc = dp.RCC.freeze(Config::hsi16());
+    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
+
+    // constructor initializes 48 MHz clock that RNG requires
+    // Initialize 48 MHz clock and RNG
+    let hsi48 = rcc.enable_hsi48(&mut syscfg, dp.CRS);
+    let mut rng = Rng::new(dp.RNG, &mut rcc, hsi48);
+
+    loop {
+        // enable starts the ADC conversions that generate the random number
+        rng.enable();
+        // wait until the flag flips; interrupt driven is possible but no implemented
+        rng.wait();
+        // reading the result clears the ready flag
+        let _ = rng.take_result();
+        // can save some power by disabling until next random number needed
+        rng.disable();
+    }
+}

src/lib.rs

@@ -33,6 +33,8 @@ pub mod prelude;
 pub mod pwm;
 pub mod pwr;
 pub mod rcc;
+#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
+pub mod rng;
 pub mod rtc;
 pub mod serial;
 pub mod spi;

src/rng.rs

@@ -0,0 +1,58 @@
+use crate::rcc::{HSI48, Rcc};
+
+pub use crate::pac::{rng, RNG};
+
+
+pub struct Rng {
+    rng: RNG
+}
+
+impl Rng {
+    // Initializes the peripheral
+    pub fn new(rng: RNG, rcc: &mut Rcc, _: HSI48) -> Rng {
+        // Reset peripheral
+        rcc.rb.ahbrstr.modify(|_, w| w.rngrst().set_bit());
+        rcc.rb.ahbrstr.modify(|_, w| w.rngrst().clear_bit());
+
+        // Enable peripheral clock
+        rcc.rb.ahbenr.modify(|_, w| w.rngen().set_bit());
+
+        rng.cr.write(|w| 
+            w
+                .rngen().set_bit()
+                .ie().clear_bit()
+        );
+
+        let mut ret = Self {
+            rng
+        };
+
+        ret.enable();
+
+        ret
+    }
+
+    pub fn enable(&mut self) {
+        self.rng.cr.write(|w| 
+            w
+                .rngen().set_bit()
+                .ie().clear_bit()
+        );
+    }
+
+    pub fn disable(&mut self) {
+        self.rng.cr.modify(|_, w| 
+            w
+                .rngen().clear_bit()
+                .ie().clear_bit()
+        );
+    }
+
+    pub fn wait(&mut self) {
+        while self.rng.sr.read().drdy().bit_is_clear() {}
+    }
+
+    pub fn take_result(&mut self) -> u32 {
+        self.rng.dr.read().bits()
+    }
+}