Merge pull request #53 from braun-embedded/rng

Add RNG API

Author: arkorobotics

Cargo.toml

@@ -114,6 +114,10 @@ required-features = ["rt"]
 name = "i2c_dma"
 required-features = ["rt","stm32l0x2"]
 
+[[example]]
+name = "rng"
+required-features = ["rt","stm32l0x2"]
+
 [[example]]
 name = "rtc"
 required-features = ["stm32l0x2"]

examples/rng.rs

@@ -0,0 +1,34 @@
+#![no_main]
+#![no_std]
+
+
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+use stm32l0xx_hal::{pac, prelude::*, rcc::Config, syscfg::SYSCFG};
+
+use stm32l0xx_hal::rng::Rng;
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+
+    let mut rcc = dp.RCC.freeze(Config::hsi16());
+    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
+
+    // constructor initializes 48 MHz clock that RNG requires
+    // Initialize 48 MHz clock and RNG
+    let hsi48 = rcc.enable_hsi48(&mut syscfg, dp.CRS);
+    let mut rng = Rng::new(dp.RNG, &mut rcc, hsi48);
+
+    loop {
+        // enable starts the ADC conversions that generate the random number
+        rng.enable();
+        // wait until the flag flips; interrupt driven is possible but no implemented
+        rng.wait();
+        // reading the result clears the ready flag
+        let _ = rng.take_result();
+        // can save some power by disabling until next random number needed
+        rng.disable();
+    }
+}

src/lib.rs

@@ -33,6 +33,8 @@ pub mod prelude;
 pub mod pwm;
 pub mod pwr;
 pub mod rcc;
+#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
+pub mod rng;
 pub mod rtc;
 pub mod serial;
 pub mod spi;

src/rcc.rs

@@ -1,6 +1,13 @@
 use crate::pac::RCC;
 use crate::time::{Hertz, U32Ext};
 
+#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
+use crate::{
+    pac::CRS,
+    syscfg::SYSCFG,
+};
+
+
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
@@ -170,6 +177,45 @@ pub struct Rcc {
     pub(crate) rb: RCC,
 }
 
+#[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
+impl Rcc {
+    pub fn enable_hsi48(&mut self, syscfg: &mut SYSCFG, crs: CRS) -> HSI48 {
+        // Reset CRS peripheral
+        self.rb.apb1rstr.modify(|_, w| w.crsrst().set_bit());
+        self.rb.apb1rstr.modify(|_, w| w.crsrst().clear_bit());
+
+        // Enable CRS peripheral
+        self.rb.apb1enr.modify(|_, w| w.crsen().set_bit());
+
+        // Initialize CRS
+        crs.cfgr.write(|w|
+            // Select LSE as synchronization source
+            unsafe { w.syncsrc().bits(0b01) }
+        );
+        crs.cr.write(|w|
+            w
+                .autotrimen().set_bit()
+                .cen().set_bit()
+        );
+
+        // Enable VREFINT reference for HSI48 oscillator
+        syscfg.syscfg.cfgr3.modify(|_, w|
+            w
+                .enref_rc48mhz().set_bit()
+                .en_bgap().set_bit()
+        );
+
+        // Select HSI48 as USB clock
+        self.rb.ccipr.modify(|_, w| w.hsi48msel().set_bit());
+
+        // Enable dedicated USB clock
+        self.rb.crrcr.modify(|_, w| w.hsi48on().set_bit());
+        while self.rb.crrcr.read().hsi48rdy().bit_is_clear() {};
+
+        HSI48(())
+    }
+}
+
 /// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
 pub trait RccExt {
     fn freeze(self, config: Config) -> Rcc;
@@ -310,6 +356,7 @@ impl RccExt for RCC {
 
         Rcc { rb: self, clocks }
     }
+
 }
 
 /// Frozen clock frequencies
@@ -362,3 +409,10 @@ impl Clocks {
         self.apb2_tim_clk
     }
 }
+
+
+/// Token that exists only, if the HSI48 clock has been enabled
+///
+/// You can get an instance of this struct by calling [`Rcc::enable_hsi48`].
+#[derive(Clone, Copy)]
+pub struct HSI48(());

src/rng.rs

@@ -0,0 +1,58 @@
+use crate::rcc::{HSI48, Rcc};
+
+pub use crate::pac::{rng, RNG};
+
+
+pub struct Rng {
+    rng: RNG
+}
+
+impl Rng {
+    // Initializes the peripheral
+    pub fn new(rng: RNG, rcc: &mut Rcc, _: HSI48) -> Rng {
+        // Reset peripheral
+        rcc.rb.ahbrstr.modify(|_, w| w.rngrst().set_bit());
+        rcc.rb.ahbrstr.modify(|_, w| w.rngrst().clear_bit());
+
+        // Enable peripheral clock
+        rcc.rb.ahbenr.modify(|_, w| w.rngen().set_bit());
+
+        rng.cr.write(|w| 
+            w
+                .rngen().set_bit()
+                .ie().clear_bit()
+        );
+
+        let mut ret = Self {
+            rng
+        };
+
+        ret.enable();
+
+        ret
+    }
+
+    pub fn enable(&mut self) {
+        self.rng.cr.write(|w| 
+            w
+                .rngen().set_bit()
+                .ie().clear_bit()
+        );
+    }
+
+    pub fn disable(&mut self) {
+        self.rng.cr.modify(|_, w| 
+            w
+                .rngen().clear_bit()
+                .ie().clear_bit()
+        );
+    }
+
+    pub fn wait(&mut self) {
+        while self.rng.sr.read().drdy().bit_is_clear() {}
+    }
+
+    pub fn take_result(&mut self) -> u32 {
+        self.rng.dr.read().bits()
+    }
+}

src/usb.rs

@@ -18,10 +18,9 @@
 //! fits together.
 
 
-use crate::{
-    pac,
-    rcc::Rcc,
-    syscfg::SYSCFG,
+use crate::rcc::{
+    HSI48,
+    Rcc,
 };
 
 
@@ -30,39 +29,7 @@ use crate::{
 /// This method takes care of the platform-specific bits of the USB
 /// initialization. After calling this method, you need `stm32-usbd` to actually
 /// do anything useful with the USB peripheral.
-pub fn init(rcc: &mut Rcc, syscfg: &mut SYSCFG, crs: pac::CRS) {
-    // Reset CRS peripheral
-    rcc.rb.apb1rstr.modify(|_, w| w.crsrst().set_bit());
-    rcc.rb.apb1rstr.modify(|_, w| w.crsrst().clear_bit());
-
-    // Enable CRS peripheral
-    rcc.rb.apb1enr.modify(|_, w| w.crsen().set_bit());
-
-    // Initialize CRS
-    crs.cfgr.write(|w|
-        // Select LSE as synchronization source
-        unsafe { w.syncsrc().bits(0b01) }
-    );
-    crs.cr.write(|w|
-        w
-            .autotrimen().set_bit()
-            .cen().set_bit()
-    );
-
-    // Enable VREFINT reference for HSI48 oscillator
-    syscfg.syscfg.cfgr3.modify(|_, w|
-        w
-            .enref_rc48mhz().set_bit()
-            .en_bgap().set_bit()
-    );
-
-    // Select HSI48 as USB clock
-    rcc.rb.ccipr.modify(|_, w| w.hsi48msel().set_bit());
-
-    // Enable dedicated USB clock
-    rcc.rb.crrcr.modify(|_, w| w.hsi48on().set_bit());
-    while rcc.rb.crrcr.read().hsi48rdy().bit_is_clear() {};
-
+pub fn init(rcc: &mut Rcc, _: HSI48) {
     // Reset USB peripheral
     rcc.rb.apb1rstr.modify(|_, w| w.usbrst().set_bit());
     rcc.rb.apb1rstr.modify(|_, w| w.usbrst().clear_bit());