Merge pull request #51 from jonas-schievink/update-stm32l0

Update to stm32l0 0.9.0

Author: arkorobotics

Cargo.toml

@@ -27,6 +27,7 @@ version = "0.4.0"
 features = ["stm32l0x2", "rt", "stm32-usbd"]
 
 [dependencies]
+stm32l0 = "0.9.0"
 as-slice = "0.1.0"
 embedded-hal = { version = "0.2.3", features = ["unproven"] }
 cortex-m = {version = "0.6.1", features = ["const-fn"] }
@@ -37,9 +38,6 @@ cast = { version = "0.2.2", default-features = false }
 nb = "0.1.2"
 stm32-usbd = { version = "0.5.0", features = ["ram_access_2x16"], optional = true }
 
-[dependencies.stm32l0]
-version = "0.8.0"
-
 [dev-dependencies]
 aligned = "0.3.1"
 heapless = "0.5.0"

examples/button_irq.rs

@@ -39,10 +39,7 @@ fn main() -> ! {
     // Configure PB2 as input.
     let button = gpiob.pb2.into_pull_up_input();
 
-    #[cfg(feature = "stm32l0x1")]
     let mut syscfg = SYSCFG::new(dp.SYSCFG, &mut rcc);
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
 
     // Configure the external interrupt on the falling edge for the pin 0.
     let exti = dp.EXTI;

examples/button_irq_rtfm.rs

@@ -28,10 +28,7 @@ const APP: () = {
         // Configure PB2 as input.
         let button = gpiob.pb2.into_pull_up_input();
 
-        #[cfg(feature = "stm32l0x1")]
         let mut syscfg = SYSCFG::new(device.SYSCFG, &mut rcc);
-        #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-        let mut syscfg = SYSCFG::new(device.SYSCFG_COMP, &mut rcc);
 
         // Configure the external interrupt on the falling edge for the pin 0.
         let exti = device.EXTI;

examples/exti_wakeup.rs

@@ -29,10 +29,7 @@ fn main() -> ! {
     let button = gpiob.pb2.into_floating_input();
     let mut led = gpiob.pb6.into_push_pull_output();
 
-    #[cfg(feature = "stm32l0x1")]
     let mut syscfg = SYSCFG::new(dp.SYSCFG, &mut rcc);
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
 
     exti.listen(
         &mut syscfg,

examples/pwr.rs

@@ -44,10 +44,7 @@ fn main() -> ! {
 
     let mut led = gpiob.pb2.into_push_pull_output().downgrade();
 
-    #[cfg(feature = "stm32l0x1")]
     let mut syscfg = SYSCFG::new(dp.SYSCFG, &mut rcc);
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
 
     let instant = Instant::new()
         .set_year(19)

examples/rng.rs

@@ -14,7 +14,7 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let mut rcc = dp.RCC.freeze(Config::hsi16());
-    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
+    let mut syscfg = SYSCFG::new(dp.SYSCFG, &mut rcc);
 
     // constructor initializes 48 MHz clock that RNG requires
     // Initialize 48 MHz clock and RNG
@@ -31,4 +31,4 @@ fn main() -> ! {
         // can save some power by disabling until next random number needed
         rng.disable();
     }
-}
+}

examples/rtc_wakeup.rs

@@ -32,10 +32,7 @@ fn main() -> ! {
     let mut exti = dp.EXTI;
     let mut pwr = PWR::new(dp.PWR, &mut rcc);
 
-    #[cfg(feature = "stm32l0x1")]
     let mut syscfg = SYSCFG::new(dp.SYSCFG, &mut rcc);
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    let mut syscfg = SYSCFG::new(dp.SYSCFG_COMP, &mut rcc);
 
     let instant = Instant::new()
         .set_year(19)

src/adc.rs

@@ -110,22 +110,12 @@ impl Adc {
         while self.rb.cr.read().aden().bit_is_set() {}
     }
 
-    #[cfg(feature = "stm32l0x1")]
     fn write_smpr(&mut self) {
         self.rb
             .smpr
             .modify(|_, w| w.smp().bits(self.sample_time as u8));
     }
 
-    #[cfg(any(feature = "stm32l0x2", feature = "stm32l0x3"))]
-    fn write_smpr(&mut self) {
-        self.rb
-            .smpr
-            // Safe, because `self.sample_time` is of type `SampleTime`, which
-            // defines only valid values.
-            .modify(|_, w| unsafe { w.smpr().bits(self.sample_time as u8) });
-    }
-
     pub fn release(self) -> ADC {
         self.rb
     }
@@ -156,8 +146,7 @@ where
             //
             // The `bits` method is not unsafe on STM32L0x1, so we need to
             // suppress the warning there.
-            #[cfg_attr(feature = "stm32l0x1", allow(unused_unsafe))]
-            let w = unsafe { w.res().bits(self.precision as u8) };
+            let w = w.res().bits(self.precision as u8);
             w.align().bit(self.align == Align::Left)
         });
 

src/aes.rs

@@ -1,4 +1,7 @@
-//! Interface to the AES peripheral
+//! Interface to the AES peripheral.
+//!
+//! Note that the AES peripheral is only available on some MCUs in the L0/L1/L2
+//! families. Check the datasheet for more information.
 //!
 //! See STM32L0x2 reference manual, chapter 18.
 
@@ -88,7 +91,7 @@ impl AES {
 
             // Configure for stream of bytes
             // Safe, as we write a valid byte pattern.
-            unsafe { w.datatype().bits(0b10) };
+            w.datatype().bits(0b10);
 
             // Enable peripheral
             w.en().set_bit()
@@ -524,7 +527,7 @@ impl Mode for CTR {
 fn derive_key(aes: &aes::RegisterBlock) {
     // Select key derivation mode. This is safe, as we're writing a valid bit
     // pattern.
-    unsafe { aes.cr.modify(|_, w| w.mode().bits(0b01)) };
+    aes.cr.modify(|_, w| w.mode().bits(0b01));
 
     // Enable the peripheral. It will be automatically disabled again once the
     // key has been derived.