From fd567a9dd008c8bad8deb32e6cf73e823b8aac55 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Mon, 11 Sep 2023 22:17:16 +0200 Subject: [PATCH] Revert "Move ethernet DMA reset slightly earlier to eliminate freeze on h723" This reverts commit c221c515027cf408eaa777e14437c10d296aaafc. --- src/ethernet/eth.rs | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/ethernet/eth.rs b/src/ethernet/eth.rs index dc51ed92..d786dac0 100644 --- a/src/ethernet/eth.rs +++ b/src/ethernet/eth.rs @@ -455,12 +455,6 @@ pub unsafe fn new_unchecked( // Ensure syscfg is enabled (for PMCR) rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); - // Reset ETH_DMA - write 1 and wait for 0. - // On the H723, we have to do this before prec.enable() - // or the DMA will never come out of reset - eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); - while eth_dma.dmamr.read().swr().bit_is_set() {} - // AHB1 ETH1MACEN prec.enable(); @@ -478,6 +472,10 @@ pub unsafe fn new_unchecked( //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit()); cortex_m::interrupt::free(|_cs| { + // reset ETH_DMA - write 1 and wait for 0 + eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); + while eth_dma.dmamr.read().swr().bit_is_set() {} + // 200 MHz eth_mac .mac1ustcr