Merge #230 #256

230: Initial OCTOSPI and QUADSPI memories support r=richardeoin a=richardeoin

`write_extended` and `read_extended` methods allow more complicated transactions, such as those needed to read/write from flash memories.

Rename the `quadspi` flag to `xspi`

Ref #165 

256: Implement IoPin r=richardeoin a=olback

Implements the IoPin trait from embedded-hal.

Co-authored-by: Richard Meadows <962920+richardeoin@users.noreply.github.com>
Co-authored-by: Alex Norman <alex@x37v.info>
Co-authored-by: Richard Meadows <richardeoin@gmail.com>
Co-authored-by: Petr Horacek <hrck@protonmail.com>
Co-authored-by: Edwin Svensson <git@olback.net>
Co-authored-by: Edwin <git@olback.net>

Author: 5 people

.github/workflows/ci.yml

@@ -23,7 +23,7 @@ jobs:
           - stm32h7b0
           - stm32h735
     env:                        # Peripheral Feature flags
-      FLAGS: rt,quadspi,sdmmc,fmc,usb_hs,rtc,ethernet,ltdc,crc
+      FLAGS: rt,xspi,sdmmc,fmc,usb_hs,rtc,ethernet,ltdc,crc
 
     steps:
       - uses: actions/checkout@v2

.github/workflows/nightly.yml

@@ -19,7 +19,7 @@ jobs:
           - log-semihost
           - log-rtt
     env:                        # Peripheral Feature flags
-      FLAGS: rt,quadspi,sdmmc,fmc,usb_hs,rtc,ethernet,ltdc,crc
+      FLAGS: rt,xspi,sdmmc,fmc,usb_hs,rtc,ethernet,ltdc,crc
 
     steps:
       - uses: actions/checkout@v2

CHANGELOG.md

@@ -29,6 +29,8 @@
 * spi: Add more hardware CS features #216
 * timers: Better calculations for `set_timeout_ticks` #208
 
+* **Breaking**: Rename the `quadspi` flag to `xspi`
+
 ## [v0.9.0] 2021-03-12
 
 * Updates `cortex-m` to v0.7.1. `cortex-m` v0.6.5+ [are forward compatible with

Cargo.toml

@@ -25,7 +25,7 @@ features = ["stm32h743v", "rt", "quadspi", "sdmmc", "fmc", "usb_hs", "rtc", "eth
 targets = ["thumbv7em-none-eabihf"]
 
 [dependencies]
-embedded-hal = "0.2.4"
+embedded-hal = "0.2.6"
 embedded-dma = "0.1.2"
 cortex-m = "^0.7.1"
 stm32h7 = "^0.14.0"
@@ -86,7 +86,7 @@ cm4 = []
 cm7 = []
 smps = []
 ltdc = ["embedded-display-controller"]
-quadspi = []
+xspi = []
 fmc = ["stm32-fmc"]
 sdmmc = ["sdio-host"]
 sdmmc-fatfs = ["embedded-sdmmc", "sdmmc"]
@@ -145,11 +145,19 @@ required-features = ["fmc", "rm0399"]
 
 [[example]]
 name = "qspi"
-required-features = ["quadspi", "rm0433"]
+required-features = ["xspi", "rm0433"]
 
 [[example]]
 name = "qspi_mdma"
-required-features = ["quadspi", "rm0433"]
+required-features = ["xspi", "rm0433"]
+
+[[example]]
+name = "qspi_flash_memory"
+required-features = ["xspi", "rm0433"]
+
+[[example]]
+name = "octospi"
+required-features = ["xspi", "rm0468"]
 
 [[example]]
 name = "sdmmc"

examples/octospi.rs

@@ -0,0 +1,98 @@
+//! OCTOSPI peripheral example in indirect mode
+//!
+//! Tested on a STM32H735G-DK with a Macronix MX25LM51245GXDI00
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+#[macro_use]
+mod utilities;
+
+use cortex_m_rt::entry;
+use stm32h7xx_hal::rcc::rec::{OctospiClkSel, OctospiClkSelGetter};
+use stm32h7xx_hal::{
+    pac, prelude::*, xspi::OctospiMode, xspi::OctospiWord as XW,
+};
+
+use log::info;
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Constrain and Freeze power
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = example_power!(pwr).freeze();
+
+    // Constrain and Freeze clock
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(96.mhz()).freeze(pwrcfg, &dp.SYSCFG);
+
+    // Octospi from HCLK at 48MHz
+    assert_eq!(ccdr.clocks.hclk().0, 48_000_000);
+    assert_eq!(
+        ccdr.peripheral.OCTOSPI1.get_kernel_clk_mux(),
+        OctospiClkSel::RCC_HCLK3
+    );
+
+    // Acquire the GPIO peripherals. This also enables the clock for
+    // the GPIOs in the RCC register.
+    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
+    let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
+    let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+    let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
+
+    let _ncs = gpiog.pg6.into_alternate_af10();
+    let _clk = gpiof.pf10.into_alternate_af9();
+    let _io0 = gpiod.pd11.into_alternate_af9();
+    let _io1 = gpiod.pd12.into_alternate_af9();
+    let _io2 = gpioe.pe2.into_alternate_af9();
+    let _io3 = gpiod.pd13.into_alternate_af9();
+    let _io4 = gpiod.pd4.into_alternate_af10();
+    let _io5 = gpiod.pd5.into_alternate_af10();
+    let _io6 = gpiog.pg9.into_alternate_af9();
+    let _io7 = gpiod.pd7.into_alternate_af10();
+
+    info!("");
+    info!("stm32h7xx-hal example - OCTOSPI");
+    info!("");
+
+    // Initialise the OCTOSPI peripheral.
+    let mut octospi = dp.OCTOSPI1.octospi_unchecked(
+        12.mhz(),
+        &ccdr.clocks,
+        ccdr.peripheral.OCTOSPI1,
+    );
+
+    octospi.configure_mode(OctospiMode::OneBit).unwrap();
+
+    // RDID Read Identification. Abuses address as instruction phase, but that
+    // works in SPI mode.
+    let mut read: [u8; 3] = [0; 3];
+    octospi.read(0x9F, &mut read).unwrap();
+    info!("Read with instruction 0x9F : {:x?}", read);
+
+    // Switch Macronix MX25LM51245GXDI00 to SDR OPI
+    // Set WREN bit
+    octospi
+        .write_extended(XW::U8(0x06), XW::None, XW::None, &[])
+        .unwrap();
+    // Write Configuration Register 2
+    octospi
+        .write_extended(XW::U8(0x72), XW::U32(0), XW::None, &[1])
+        .unwrap();
+    // Change bus mode
+    octospi.configure_mode(OctospiMode::EightBit).unwrap();
+
+    // RDID Read Identification
+    let mut read: [u8; 3] = [0; 3];
+    octospi
+        .read_extended(XW::U16(0x9F60), XW::U32(0), XW::None, 4, &mut read)
+        .unwrap();
+
+    info!("Read with instruction 0x9F60 : {:x?}", read);
+
+    loop {}
+}

examples/qspi.rs

@@ -6,7 +6,7 @@
 mod utilities;
 
 use cortex_m_rt::entry;
-use stm32h7xx_hal::{pac, prelude::*, qspi::QspiMode};
+use stm32h7xx_hal::{pac, prelude::*, xspi::QspiMode};
 
 use log::info;
 

examples/qspi_flash_memory.rs

@@ -0,0 +1,188 @@
+//! Example of communication with flash memory over QSPI interface. This
+//! specific program is made for Daisy Seed board and its IS25LP064A flash
+//! memory chip. This demo provides a non-volatile restart counter. When it is
+//! odd, LED will light up, when even, it stays off.
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+#[macro_use]
+mod utilities;
+
+use core::mem::transmute;
+
+use cortex_m_rt::entry;
+use stm32h7xx_hal::gpio::Speed;
+use stm32h7xx_hal::hal::digital::v2::OutputPin;
+use stm32h7xx_hal::{
+    pac, prelude::*, xspi::Qspi, xspi::QspiMode, xspi::QspiWord,
+};
+
+use log::info;
+
+// SPI commands from IS25LP064 datasheet
+const WRITE_STATUS_REGISTRY_CMD: u8 = 0x01; // WRSR
+const WRITE_CMD: u8 = 0x02; // PP
+const NORMAL_READ_CMD: u8 = 0x03; // NORD
+const READ_STATUS_REGISTRY_CMD: u8 = 0x05; // RDSR
+const WRITE_ENABLE_CMD: u8 = 0x06; // WREN
+const SET_READ_PARAMETERS_CMD: u8 = 0xC0; // SRP
+const SECTOR_ERASE_CMD: u8 = 0xD8; // SER
+
+// Address in the external memory that will be used for the counter
+const COUNTER_ADDRESS: u32 = 0x00;
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Constrain and Freeze power
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = example_power!(pwr).freeze();
+
+    // Constrain and Freeze clock
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(96.mhz()).freeze(pwrcfg, &dp.SYSCFG);
+
+    // Acquire the GPIO peripherals
+    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
+    let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
+    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
+
+    // Even though it is not directly used, CS pin must be acquired and configured
+    let _qspi_cs = gpiog.pg6.into_alternate_af10().set_speed(Speed::VeryHigh);
+
+    let sck = gpiof.pf10.into_alternate_af9().set_speed(Speed::VeryHigh);
+    let io0 = gpiof.pf8.into_alternate_af10().set_speed(Speed::VeryHigh);
+    let io1 = gpiof.pf9.into_alternate_af10().set_speed(Speed::VeryHigh);
+    let io2 = gpiof.pf7.into_alternate_af9().set_speed(Speed::VeryHigh);
+    let io3 = gpiof.pf6.into_alternate_af9().set_speed(Speed::VeryHigh);
+
+    let mut led = gpioc.pc7.into_push_pull_output();
+
+    info!("");
+    info!("stm32h7xx-hal example - QSPI Flash Memory");
+    info!("");
+
+    // Initialise the QSPI peripheral
+    let mut qspi = dp.QUADSPI.bank1(
+        (sck, io0, io1, io2, io3),
+        3.mhz(),
+        &ccdr.clocks,
+        ccdr.peripheral.QSPI,
+    );
+    qspi.configure_mode(QspiMode::OneBit).unwrap();
+
+    // Reset configuration of the flash memory
+    reset_status_registry(&mut qspi);
+    reset_read_registry(&mut qspi);
+
+    // Read the current value and increment it
+    let original = read_u32(&mut qspi, COUNTER_ADDRESS);
+    write_u32(&mut qspi, COUNTER_ADDRESS, original.overflowing_add(1).0);
+
+    // Based on the original value, enable or disable LED on the board
+    if original % 2 == 0 {
+        led.set_low().unwrap();
+    } else {
+        led.set_high().unwrap();
+    }
+
+    loop {
+        cortex_m::asm::nop();
+    }
+}
+
+fn read_u32(qspi: &mut Qspi<pac::QUADSPI>, address: u32) -> u32 {
+    let mut buffer: [u8; 4] = [0xFF; 4];
+    qspi.read_extended(
+        QspiWord::U8(NORMAL_READ_CMD),
+        QspiWord::U24(address),
+        QspiWord::None,
+        0,
+        &mut buffer,
+    )
+    .unwrap();
+    u32::from_be_bytes(buffer)
+}
+
+fn write_u32(qspi: &mut Qspi<pac::QUADSPI>, address: u32, value: u32) {
+    enable_write_operation(qspi);
+    qspi.write_extended(
+        QspiWord::U8(SECTOR_ERASE_CMD),
+        QspiWord::U24(address),
+        QspiWord::None,
+        &[],
+    )
+    .unwrap();
+    wait_for_write_completition(qspi);
+
+    let bytes: [u8; 4] = unsafe { transmute(value.to_be()) };
+    enable_write_operation(qspi);
+    qspi.write_extended(
+        QspiWord::U8(WRITE_CMD),
+        QspiWord::U24(address),
+        QspiWord::None,
+        &bytes,
+    )
+    .unwrap();
+    wait_for_write_completition(qspi);
+}
+
+fn reset_status_registry(qspi: &mut Qspi<pac::QUADSPI>) {
+    enable_write_operation(qspi);
+
+    qspi.write_extended(
+        QspiWord::U8(WRITE_STATUS_REGISTRY_CMD),
+        QspiWord::U8(0b00000000),
+        QspiWord::None,
+        &[],
+    )
+    .unwrap();
+
+    wait_for_write_completition(qspi);
+}
+
+fn reset_read_registry(qspi: &mut Qspi<pac::QUADSPI>) {
+    enable_write_operation(qspi);
+
+    qspi.write_extended(
+        QspiWord::U8(SET_READ_PARAMETERS_CMD),
+        QspiWord::U8(0b11100000),
+        QspiWord::None,
+        &[],
+    )
+    .unwrap();
+
+    wait_for_write_completition(qspi);
+}
+
+fn enable_write_operation(qspi: &mut Qspi<pac::QUADSPI>) {
+    qspi.write_extended(
+        QspiWord::U8(WRITE_ENABLE_CMD),
+        QspiWord::None,
+        QspiWord::None,
+        &[],
+    )
+    .unwrap();
+}
+
+fn wait_for_write_completition(qspi: &mut Qspi<pac::QUADSPI>) {
+    loop {
+        let mut status: [u8; 1] = [0xFF; 1];
+        qspi.read_extended(
+            QspiWord::U8(READ_STATUS_REGISTRY_CMD),
+            QspiWord::None,
+            QspiWord::None,
+            0,
+            &mut status,
+        )
+        .unwrap();
+
+        if status[0] & 0x01 == 0 {
+            break;
+        }
+    }
+}

examples/qspi_mdma.rs

@@ -13,7 +13,7 @@ mod utilities;
 use core::mem;
 
 use cortex_m_rt::entry;
-use stm32h7xx_hal::{pac, prelude::*, qspi, qspi::QspiMode};
+use stm32h7xx_hal::{pac, prelude::*, xspi, xspi::QspiMode};
 
 use stm32h7xx_hal::dma::{
     mdma::{
@@ -57,7 +57,7 @@ fn main() -> ! {
     info!("stm32h7xx-hal example - QSPI with MDMA");
     info!("");
 
-    let config: qspi::Config = 1.mhz().into();
+    let config: xspi::Config = 1.mhz().into();
     // Threshold when half full
     let config = config.fifo_threshold(16);