Skip to content

Commit ab2854f

Browse files
bors[bot]richardeoin
bors[bot]
and
richardeoin
authored
Merge #240
240: Update to stm32-rs v0.14.0 r=richardeoin a=richardeoin * ~RTIC v0.5 is no longer supported since the PAC does not implement `Nr` trait for Interrupts~ * RCC registers have been renamed for RM0455 parts * PAC `Variant::Val<T>` replaced with `Option<T>` Co-authored-by: Richard Meadows <962920+richardeoin@users.noreply.github.com>
2 parents 7e6652e + 4b00047 commit ab2854f

File tree

19 files changed

+228
-186
lines changed

19 files changed

+228
-186
lines changed

‎CHANGELOG.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@
1010
* **Breaking**: Simplified API for reading device signature
1111
values. `VAL::get().read()` becomes `VAL::read()`
1212
* adc: Allow parallel execution of multiple ADCs through `start_conversion()`
13+
* Rename the PeripheralREC object for BDMA2 on 7B3, 7B0, 7A3 parts from BDMA to BDMA2
14+
* pac: Upgrade to stm32-rs v0.14.0
1315

1416
## [v0.10.0] 2021-07-xx
1517

‎Cargo.toml

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,8 @@ targets = ["thumbv7em-none-eabihf"]
2828
embedded-hal = "0.2.4"
2929
embedded-dma = "0.1.2"
3030
cortex-m = "^0.7.1"
31-
cortex-m-rt = "^0.6.12"
32-
stm32h7 = "^0.13.0"
31+
cortex-m-rt = "^0.6.15"
32+
stm32h7 = "^0.14.0"
3333
void = { version = "1.0.2", default-features = false }
3434
cast = { version = "0.2.3", default-features = false }
3535
nb = "1.0.0"
@@ -52,12 +52,12 @@ default-features = false
5252
optional = true
5353

5454
[dev-dependencies]
55-
cortex-m-rtic = "0.5.3"
55+
cortex-m-rtic = { version = "0.5.8", default-features = false, features = ["cortex-m-7"] }
5656
log = "0.4.11"
5757
panic-halt = "0.2.0"
58-
cfg-if = "0.1.10"
59-
rtt-target = { version = "0.2.0", features = ["cortex-m"] }
6058
panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] }
59+
cfg-if = "1.0.0"
60+
rtt-target = { version = "0.3.1", features = ["cortex-m"] }
6161
lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
6262
cortex-m-log = { version = "~0.7.0", features = ["itm", "semihosting", "log-integration"] }
6363
panic-itm = { version = "~0.4.1" }

‎examples/i2c4_bdma.rs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,10 @@ fn main() -> ! {
3737
let dp = pac::Peripherals::take().expect("Cannot take peripherals");
3838

3939
// Run D3 / SRD domain
40+
#[cfg(not(feature = "rm0455"))]
4041
dp.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
42+
#[cfg(feature = "rm0455")]
43+
dp.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
4144

4245
let pwr = dp.PWR.constrain();
4346
let pwrcfg = example_power!(pwr).freeze();
@@ -84,7 +87,7 @@ fn main() -> ! {
8487
#[cfg(feature = "rm0455")]
8588
let streams = StreamsTuple::new(
8689
dp.BDMA2,
87-
ccdr.peripheral.BDMA.low_power(LowPowerMode::Autonomous),
90+
ccdr.peripheral.BDMA2.low_power(LowPowerMode::Autonomous),
8891
);
8992

9093
let config = BdmaConfig::default().memory_increment(true);

‎examples/rtic_low_power.rs

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,10 @@
33
//! After the end of init the CPU transitions into CStop mode, and D1/D2
44
//! (aka. CD) transition into DStop mode.
55
//!
6-
//! However we set the run_d3 flag, and enable Autonomous mode on the LPTIM3
7-
//! PREC struture. Therefore LPTIM3 continues to run and fires an interrupt that
8-
//! wakes the core. Following each interrupt the core returns to CStop mode.
6+
//! However we set the run_d3/run_srd flag, and enable Autonomous mode on the
7+
//! LPTIM3 PREC struture. Therefore LPTIM3 continues to run and fires an
8+
//! interrupt that wakes the core. Following each interrupt the core returns to
9+
//! CStop mode.
910
//!
1011
//! On the first rising edge on PC13, the EXTI interrupt fires. We do not clear
1112
//! this interrupt, so we loop in the handler forever.
@@ -47,7 +48,10 @@ const APP: () = {
4748
let mut syscfg = ctx.device.SYSCFG;
4849

4950
// Run D3 / SRD domain
51+
#[cfg(not(feature = "rm0455"))]
5052
ctx.device.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
53+
#[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
54+
ctx.device.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
5155

5256
let pwr = ctx.device.PWR.constrain();
5357
let vos = pwr.freeze();

‎src/adc.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@ use crate::gpio::Analog;
2929
use crate::rcc::rec::AdcClkSelGetter;
3030
use crate::rcc::{rec, CoreClocks, ResetEnable};
3131
use crate::time::Hertz;
32-
use stm32h7::Variant::Val;
3332

3433
#[cfg(not(feature = "revision_v"))]
3534
const ADC_KER_CK_MAX: u32 = 36_000_000;
@@ -324,9 +323,9 @@ pub struct StoredConfig(AdcSampleTime, Resolution, AdcLshift);
324323
fn check_clock(prec: &impl AdcClkSelGetter, clocks: &CoreClocks) -> Hertz {
325324
// Select Kernel Clock
326325
let adc_clock = match prec.get_kernel_clk_mux() {
327-
Val(rec::AdcClkSel::PLL2_P) => clocks.pll2_p_ck(),
328-
Val(rec::AdcClkSel::PLL3_R) => clocks.pll3_r_ck(),
329-
Val(rec::AdcClkSel::PER) => clocks.per_ck(),
326+
Some(rec::AdcClkSel::PLL2_P) => clocks.pll2_p_ck(),
327+
Some(rec::AdcClkSel::PLL3_R) => clocks.pll3_r_ck(),
328+
Some(rec::AdcClkSel::PER) => clocks.per_ck(),
330329
_ => unreachable!(),
331330
}
332331
.expect("adc_ker_ck_input is not running!");

‎src/crc.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,18 +57,18 @@ impl Crc {
5757
let mut words = data.chunks_exact(4);
5858
for word in words.by_ref() {
5959
let word = u32::from_be_bytes(word.try_into().unwrap());
60-
self.reg.dr_mut().write(|w| w.dr().bits(word));
60+
self.reg.dr().write(|w| w.dr().bits(word));
6161
}
6262

6363
// there will be at most 3 bytes remaining, so 1 half-word and 1 byte
6464
let mut half_word = words.remainder().chunks_exact(2);
6565
if let Some(half_word) = half_word.next() {
6666
let half_word = u16::from_be_bytes(half_word.try_into().unwrap());
67-
self.reg.dr16_mut().write(|w| w.dr16().bits(half_word));
67+
self.reg.dr16().write(|w| w.dr16().bits(half_word));
6868
}
6969

7070
if let Some(byte) = half_word.remainder().first() {
71-
self.reg.dr8_mut().write(|w| w.dr8().bits(*byte));
71+
self.reg.dr8().write(|w| w.dr8().bits(*byte));
7272
}
7373
}
7474

‎src/dma/bdma.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ impl Instance for BDMA {
7070

7171
#[cfg(feature = "rm0455")]
7272
impl Instance for BDMA2 {
73-
type Rec = rec::Bdma;
73+
type Rec = rec::Bdma2;
7474

7575
#[inline(always)]
7676
fn ptr() -> *const BDMARegisterBlock {

‎src/lib.rs

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -80,8 +80,6 @@ pub mod traits;
8080
pub use nb;
8181
pub use nb::block;
8282

83-
pub use stm32h7::Variant;
84-
8583
// Single core
8684
#[cfg(any(
8785
feature = "stm32h742",

‎src/ltdc.rs

Lines changed: 38 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -125,93 +125,45 @@ impl DisplayController for Ltdc {
125125
.bit(config.pixel_clock_pol)
126126
});
127127

128-
// TODO: remove when fixed upstream
129-
// unsafe: bit ranges not defined for fields
130-
#[cfg(feature = "rm0399")]
131-
unsafe {
132-
// Set synchronization pulse width
133-
self.ltdc.sscr.modify(|_, w| {
134-
w.vsh()
135-
.bits(config.v_sync - 1)
136-
.hsw()
137-
.bits(config.h_sync - 1)
138-
});
139-
140-
// Set accumulated back porch
141-
self.ltdc.bpcr.modify(|_, w| {
142-
w.avbp()
143-
.bits(config.v_sync + config.v_back_porch - 1)
144-
.ahbp()
145-
.bits(config.h_sync + config.h_back_porch - 1)
146-
});
147-
148-
// Set accumulated active width
149-
let aa_height =
150-
config.v_sync + config.v_back_porch + config.active_height - 1;
151-
let aa_width =
152-
config.h_sync + config.h_back_porch + config.active_width - 1;
153-
self.ltdc
154-
.awcr
155-
.modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
156-
157-
// Set total width and height
158-
let total_height: u16 = config.v_sync
159-
+ config.v_back_porch
160-
+ config.active_height
161-
+ config.v_front_porch
162-
- 1;
163-
let total_width: u16 = config.h_sync
164-
+ config.h_back_porch
165-
+ config.active_width
166-
+ config.h_front_porch
167-
- 1;
168-
self.ltdc.twcr.modify(|_, w| {
169-
w.totalh().bits(total_height).totalw().bits(total_width)
170-
});
171-
}
128+
// Set synchronization pulse width
129+
self.ltdc.sscr.modify(|_, w| {
130+
w.vsh()
131+
.bits(config.v_sync - 1)
132+
.hsw()
133+
.bits(config.h_sync - 1)
134+
});
172135

173-
#[cfg(not(feature = "rm0399"))]
174-
{
175-
// Set synchronization pulse width
176-
self.ltdc.sscr.modify(|_, w| {
177-
w.vsh()
178-
.bits(config.v_sync - 1)
179-
.hsw()
180-
.bits(config.h_sync - 1)
181-
});
182-
183-
// Set accumulated back porch
184-
self.ltdc.bpcr.modify(|_, w| {
185-
w.avbp()
186-
.bits(config.v_sync + config.v_back_porch - 1)
187-
.ahbp()
188-
.bits(config.h_sync + config.h_back_porch - 1)
189-
});
190-
191-
// Set accumulated active width
192-
let aa_height =
193-
config.v_sync + config.v_back_porch + config.active_height - 1;
194-
let aa_width =
195-
config.h_sync + config.h_back_porch + config.active_width - 1;
196-
self.ltdc
197-
.awcr
198-
.modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
199-
200-
// Set total width and height
201-
let total_height: u16 = config.v_sync
202-
+ config.v_back_porch
203-
+ config.active_height
204-
+ config.v_front_porch
205-
- 1;
206-
let total_width: u16 = config.h_sync
207-
+ config.h_back_porch
208-
+ config.active_width
209-
+ config.h_front_porch
210-
- 1;
211-
self.ltdc.twcr.modify(|_, w| {
212-
w.totalh().bits(total_height).totalw().bits(total_width)
213-
});
214-
}
136+
// Set accumulated back porch
137+
self.ltdc.bpcr.modify(|_, w| {
138+
w.avbp()
139+
.bits(config.v_sync + config.v_back_porch - 1)
140+
.ahbp()
141+
.bits(config.h_sync + config.h_back_porch - 1)
142+
});
143+
144+
// Set accumulated active width
145+
let aa_height =
146+
config.v_sync + config.v_back_porch + config.active_height - 1;
147+
let aa_width =
148+
config.h_sync + config.h_back_porch + config.active_width - 1;
149+
self.ltdc
150+
.awcr
151+
.modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
152+
153+
// Set total width and height
154+
let total_height: u16 = config.v_sync
155+
+ config.v_back_porch
156+
+ config.active_height
157+
+ config.v_front_porch
158+
- 1;
159+
let total_width: u16 = config.h_sync
160+
+ config.h_back_porch
161+
+ config.active_width
162+
+ config.h_front_porch
163+
- 1;
164+
self.ltdc.twcr.modify(|_, w| {
165+
w.totalh().bits(total_height).totalw().bits(total_width)
166+
});
215167

216168
// Set the background color value
217169
self.ltdc.bccr.reset();

0 commit comments

Comments
 (0)