Merge pull request #512 from usbalbin/clippy

richardeoin · web-flow · commit 97db8f06ea06 · 2024-12-11T22:43:55.000+01:00
Fix some clippy warnings
diff --git a/examples/mdma.rs b/examples/mdma.rs
@@ -195,7 +195,9 @@ fn main() -> ! {
         Transfer::init_master(
             streams.1,
             MemoryToMemory::new(),
-            unsafe { mem::transmute(&mut target_buffer[..]) }, // Dest: TCM (stack)
+            unsafe {
+                mem::transmute::<&mut [u8], &mut [u8]>(&mut target_buffer[..])
+            }, // Dest: TCM (stack)
             Some(source_buffer), // Source: TCM (stack)
             config,
         )
diff --git a/examples/qspi_mdma.rs b/examples/qspi_mdma.rs
@@ -108,8 +108,10 @@ fn main() -> ! {
         _,
     > = Transfer::init_master(
         streams.0,
-        qspi,                                          // Dest: QSPI
-        unsafe { mem::transmute(&mut source_buffer) }, // Source: TCM (stack)
+        qspi, // Dest: QSPI
+        unsafe {
+            mem::transmute::<&mut [u8; 80], &mut [u8; 80]>(&mut source_buffer)
+        }, // Source: TCM (stack)
         None,
         config,
     );
diff --git a/src/adc.rs b/src/adc.rs
@@ -597,7 +597,7 @@ macro_rules! adc_hal {
                     #[cfg(not(feature = "revision_v"))]
                     let f_target = f_adc.raw();
 
-                    let (divider, presc) = match (ker_ck.raw() + f_target - 1) / f_target {
+                    let (divider, presc) = match ker_ck.raw().div_ceil(f_target) {
                         1 => (1, PRESC_A::Div1),
                         2 => (2, PRESC_A::Div2),
                         3..=4 => (4, PRESC_A::Div4),
diff --git a/src/delay.rs b/src/delay.rs
@@ -110,7 +110,7 @@ impl<'a> Countdown<'a> {
     }
 }
 
-impl<'a> CountDown for Countdown<'a> {
+impl CountDown for Countdown<'_> {
     type Time = fugit::MicrosDurationU32;
 
     fn start<T>(&mut self, count: T)
diff --git a/src/dma/mod.rs b/src/dma/mod.rs
@@ -992,9 +992,9 @@ where
     /// MDMA block. The length is referred to the source size
     ///
     /// * `s_len`: The number of input words of s_size available. `None` if the
-    /// source is a peripheral
+    ///   source is a peripheral
     /// * `d_len`: The number of input words of d_size available. `None` if the
-    /// destination is a peripheral
+    ///   destination is a peripheral
     ///
     /// `s_len` and `d_len` cannot both be peripherals (None)
     fn m_number_of_bytes(
@@ -1052,24 +1052,24 @@ where
     /// # Panics
     ///
     /// * When a memory-memory transfer is specified but the `second_buf`
-    /// argument is `None`.
+    ///   argument is `None`.
     ///
     /// * When the length is greater than 65536 bytes.
     ///
     /// * When `config` specifies a `source_increment` that is smaller than the
-    /// source size.
+    ///   source size.
     ///
     /// * When `config` specifies a `destination_increment` that is smaller than
-    /// the destination size.
+    ///   the destination size.
     ///
     /// * When `config` specifies a `transfer_length` that is not a multiple of
-    /// both the source and destination sizes.
+    ///   both the source and destination sizes.
     ///
     /// * When `config` specifies a `packing_alignment` that extends the source,
-    /// but the source size is larger than the destination size.
+    ///   but the source size is larger than the destination size.
     ///
     /// * When `config` specifies a `packing_alignment` that truncates the
-    /// source, but the source size is smaller than the destination size.
+    ///   source, but the source size is smaller than the destination size.
     pub fn init_master(
         mut stream: STREAM,
         peripheral: PERIPHERAL,
diff --git a/src/dma/traits.rs b/src/dma/traits.rs
@@ -193,7 +193,6 @@ pub trait MasterStream: Stream + Sealed {
     /// # Safety
     ///
     /// Must have the same alignment as configured for the transfer
-
     unsafe fn set_source_address(&mut self, value: usize);
 
     /// Set the destination for the Master DMA stream
diff --git a/src/ethernet/eth.rs b/src/ethernet/eth.rs
@@ -802,7 +802,7 @@ impl StationManagement for EthernetMAC {
 /// Define TxToken type and implement consume method
 pub struct TxToken<'a, const TD: usize>(&'a mut TDesRing<TD>);
 
-impl<'a, const TD: usize> phy::TxToken for TxToken<'a, TD> {
+impl<const TD: usize> phy::TxToken for TxToken<'_, TD> {
     fn consume<R, F>(self, len: usize, f: F) -> R
     where
         F: FnOnce(&mut [u8]) -> R,
@@ -818,7 +818,7 @@ impl<'a, const TD: usize> phy::TxToken for TxToken<'a, TD> {
 /// Define RxToken type and implement consume method
 pub struct RxToken<'a, const RD: usize>(&'a mut RDesRing<RD>);
 
-impl<'a, const RD: usize> phy::RxToken for RxToken<'a, RD> {
+impl<const RD: usize> phy::RxToken for RxToken<'_, RD> {
     fn consume<R, F>(self, f: F) -> R
     where
         F: FnOnce(&[u8]) -> R,
diff --git a/src/flash/operations.rs b/src/flash/operations.rs
@@ -270,10 +270,10 @@ impl UnlockedFlashBank<'_> {
     }
 }
 
-impl<'a> ErrorType for UnlockedFlashBank<'a> {
+impl ErrorType for UnlockedFlashBank<'_> {
     type Error = Error;
 }
-impl<'a> ReadNorFlash for UnlockedFlashBank<'a> {
+impl ReadNorFlash for UnlockedFlashBank<'_> {
     const READ_SIZE: usize = 1;
 
     fn read(
@@ -291,7 +291,7 @@ impl<'a> ReadNorFlash for UnlockedFlashBank<'a> {
     }
 }
 
-impl<'a> NorFlash for UnlockedFlashBank<'a> {
+impl NorFlash for UnlockedFlashBank<'_> {
     const WRITE_SIZE: usize = super::WRITE_SIZE;
     const ERASE_SIZE: usize = super::SECTOR_SIZE;
 
diff --git a/src/fmc.rs b/src/fmc.rs
@@ -125,9 +125,7 @@ impl FmcExt for stm32::FMC {
 
         // Calculate kernel clock
         let fmc_ker_ck = match clk_sel {
-            rec::FmcClkSel::RccHclk3 => {
-                Some(clocks.hclk()).expect("FMC: HCLK must be enabled")
-            }
+            rec::FmcClkSel::RccHclk3 => clocks.hclk(),
             rec::FmcClkSel::Pll1Q => {
                 clocks.pll1_q_ck().expect("FMC: PLL1_Q must be enabled")
             }
diff --git a/src/gpio.rs b/src/gpio.rs
@@ -27,14 +27,14 @@
 //! - **Dynamic**: Pin mode is selected at runtime. See changing configurations for more details
 //! - Input
 //!     - **PullUp**: Input connected to high with a weak pull up resistor. Will be high when nothing
-//!     is connected
+//!       is connected
 //!     - **PullDown**: Input connected to high with a weak pull up resistor. Will be low when nothing
-//!     is connected
+//!       is connected
 //!     - **Floating**: Input not pulled to high or low. Will be undefined when nothing is connected
 //! - Output
 //!     - **PushPull**: Output which either drives the pin high or low
 //!     - **OpenDrain**: Output which leaves the gate floating, or pulls it do ground in drain
-//!     mode. Can be used as an input in the `open` configuration
+//!       mode. Can be used as an input in the `open` configuration
 //!
 //! ## Changing modes
 //! The simplest way to change the pin mode is to use the `into_<mode>` functions. These return a
diff --git a/src/lib.rs b/src/lib.rs
@@ -111,8 +111,6 @@ pub use stm32h7::stm32h753v as stm32;
 // Dual core
 #[cfg(feature = "stm32h747cm7")]
 pub use stm32h7::stm32h747cm7 as stm32;
-#[cfg(feature = "stm32h757cm7")]
-pub use stm32h7::stm32h757cm7 as stm32;
 // TODO(rm0399): soundness of PeripheralREC macro in rcc/rec.rs
 
 // High Memory Integration
diff --git a/src/qei.rs b/src/qei.rs
@@ -186,7 +186,7 @@ macro_rules! tim_hal {
                     tim.smcr.write(|w| { w.sms().bits(3) });
 
                     #[allow(unused_unsafe)] // method is safe for some timers
-                    tim.arr.write(|w| unsafe { w.bits(core::u32::MAX) });
+                    tim.arr.write(|w| unsafe { w.bits(u32::MAX) });
                     tim.cr1.write(|w| w.cen().set_bit());
 
                     Qei { tim }
diff --git a/src/rcc/mco.rs b/src/rcc/mco.rs
@@ -44,7 +44,7 @@ macro_rules! calculate_prescaler {
             // Running?
             if let Some(freq) = self.frequency {
                 // Calculate prescaler
-                let prescaler = match (in_ck + freq - 1) / freq {
+                let prescaler = match in_ck.div_ceil(freq) {
                     0 => unreachable!(),
                     x @ 1..=15 => x,
                     _ => {
diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs
@@ -35,10 +35,10 @@
 //! * `use_hse(a)` implies `sys_ck(a)`
 //!
 //! * `sys_ck(b)` implies `pll1_p_ck(b)` unless `b` equals HSI or
-//! `use_hse(b)` was specified
+//!   `use_hse(b)` was specified
 //!
 //! * `pll1_p_ck(c)` implies `pll1_r_ck(c/2)`, including when
-//! `pll1_p_ck` was implied by `sys_ck(c)` or `mco2_from_pll1_p_ck(c)`.
+//!   `pll1_p_ck` was implied by `sys_ck(c)` or `mco2_from_pll1_p_ck(c)`.
 //!
 //! Implied clock specifications can always be overridden by explicitly
 //! specifying that clock. If this results in a configuration that cannot
@@ -416,7 +416,7 @@ macro_rules! ppre_calculate {
                 .unwrap_or_else(|| core::cmp::min($max, $hclk / 2));
 
             // Calculate suitable divider
-            let ($bits, $ppre) = match ($hclk + $pclk - 1) / $pclk
+            let ($bits, $ppre) = match $hclk.div_ceil($pclk)
             {
                 0 => unreachable!(),
                 1 => (0b000, 1 as u8),
@@ -763,19 +763,18 @@ impl Rcc {
         assert!(rcc_hclk <= rcc_hclk_max);
 
         // Estimate divisor
-        let (hpre_bits, hpre_div) =
-            match (sys_d1cpre_ck + rcc_hclk - 1) / rcc_hclk {
-                0 => unreachable!(),
-                1 => (HPRE::Div1, 1),
-                2 => (HPRE::Div2, 2),
-                3..=5 => (HPRE::Div4, 4),
-                6..=11 => (HPRE::Div8, 8),
-                12..=39 => (HPRE::Div16, 16),
-                40..=95 => (HPRE::Div64, 64),
-                96..=191 => (HPRE::Div128, 128),
-                192..=383 => (HPRE::Div256, 256),
-                _ => (HPRE::Div512, 512),
-            };
+        let (hpre_bits, hpre_div) = match sys_d1cpre_ck.div_ceil(rcc_hclk) {
+            0 => unreachable!(),
+            1 => (HPRE::Div1, 1),
+            2 => (HPRE::Div2, 2),
+            3..=5 => (HPRE::Div4, 4),
+            6..=11 => (HPRE::Div8, 8),
+            12..=39 => (HPRE::Div16, 16),
+            40..=95 => (HPRE::Div64, 64),
+            96..=191 => (HPRE::Div128, 128),
+            192..=383 => (HPRE::Div256, 256),
+            _ => (HPRE::Div512, 512),
+        };
 
         // Calculate real AXI and AHB clock
         let rcc_hclk = sys_d1cpre_ck / hpre_div;
diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs
@@ -347,7 +347,7 @@ fn calc_ck_div(
     vco_ck: u32,
     target_ck: u32,
 ) -> u32 {
-    let mut div = (vco_ck + target_ck - 1) / target_ck;
+    let mut div = vco_ck.div_ceil(target_ck);
     // If the divider takes us under the target clock, then increase it
     if strategy == PllConfigStrategy::FractionalNotLess
         && target_ck * div > vco_ck
diff --git a/src/sai/pdm.rs b/src/sai/pdm.rs
@@ -41,12 +41,20 @@ pub trait PulseDensityPins<SAI> {
     const ENABLE_BITSTREAM_CLOCK_4: bool = false;
 }
 pub trait PulseDensityPinD1<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinD2<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinD3<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinD4<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinCK1<SAI> {}
+
+#[allow(dead_code)]
 pub trait PulseDensityPinCK2<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinCK3<SAI> {}
+#[allow(dead_code)]
 pub trait PulseDensityPinCK4<SAI> {}
 
 // Pin sets
diff --git a/src/sdmmc.rs b/src/sdmmc.rs
@@ -435,7 +435,7 @@ impl<S, P: SdmmcPeripheral> Sdmmc<S, P> {
     /// Returns `(clk_div, clk_f)`, where `clk_div` is the divisor register
     /// value and `clk_f` is the resulting new clock frequency.
     fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(u16, Hertz), Error> {
-        match (ker_ck.raw() + sdmmc_ck - 1) / sdmmc_ck {
+        match ker_ck.raw().div_ceil(sdmmc_ck) {
             0 | 1 => Ok((0, ker_ck)),
             x @ 2..=2046 => {
                 let clk_div = ((x + 1) / 2) as u16;
diff --git a/src/spi.rs b/src/spi.rs
@@ -201,7 +201,7 @@ impl Config {
     ///
     /// Note:
     /// * This function updates the HAL peripheral to treat the pin provided in the MISO parameter
-    /// as the MOSI pin and the pin provided in the MOSI parameter as the MISO pin.
+    ///   as the MOSI pin and the pin provided in the MOSI parameter as the MISO pin.
     #[must_use]
     pub fn swap_mosi_miso(mut self) -> Self {
         self.swap_miso_mosi = true;
@@ -251,7 +251,7 @@ pub struct HardwareCS {
     ///
     /// Note:
     /// * This value introduces a delay on SCK from the initiation of the transaction. The delay
-    /// is specified as a number of SCK cycles, so the actual delay may vary.
+    ///   is specified as a number of SCK cycles, so the actual delay may vary.
     pub assertion_delay: f32,
     /// The polarity of the CS pin.
     pub polarity: Polarity,
@@ -274,8 +274,8 @@ pub enum HardwareCSMode {
     ///
     /// Note:
     /// * This mode does require some maintenance. Before sending, you must setup
-    /// the frame with [Spi::setup_transaction]. After everything has been sent,
-    /// you must also clean it up with [Spi::end_transaction].
+    ///   the frame with [Spi::setup_transaction]. After everything has been sent,
+    ///   you must also clean it up with [Spi::end_transaction].
     FrameTransaction,
 }
 
@@ -716,7 +716,7 @@ macro_rules! spi {
 
                         let spi_freq = freq.raw();
 	                    let spi_ker_ck = Self::kernel_clk_unwrap(clocks).raw();
-                        let mbr = match (spi_ker_ck + spi_freq - 1) / spi_freq {
+                        let mbr = match spi_ker_ck.div_ceil(spi_freq) {
                             1..=2 => MBR::Div2,
                             3..=4 => MBR::Div4,
                             5..=8 => MBR::Div8,
diff --git a/src/time.rs b/src/time.rs
@@ -6,9 +6,6 @@ pub use fugit::{
     NanosDurationU32 as NanoSeconds,
 };
 
-//use core::time::Duration;
-use cortex_m::peripheral::DWT;
-
 /// Bits per second
 pub type Bps = Hertz;
 
@@ -23,69 +20,3 @@ impl U32Ext for u32 {
         Bps::from_raw(self)
     }
 }
-
-/*
-// Implement conversion from time periods into core::time::Duration
-impl From<MilliSeconds> for Duration {
-    fn from(ms: MilliSeconds) -> Self {
-        Self::from_millis(ms.0 as u64)
-    }
-}
-
-impl From<MicroSeconds> for Duration {
-    fn from(us: MicroSeconds) -> Self {
-        Self::from_micros(us.0 as u64)
-    }
-}
-
-impl From<NanoSeconds> for Duration {
-    fn from(ns: NanoSeconds) -> Self {
-        Self::from_nanos(ns.0 as u64)
-    }
-}
-*/
-
-// /// A monotonic nondecreasing timer
-// #[derive(Clone, Copy)]
-// pub struct MonoTimer {
-//     frequency: Hertz,
-// }
-
-// impl MonoTimer {
-//     /// Creates a new `Monotonic` timer
-//     pub fn new(mut dwt: DWT, clocks: Clocks) -> Self {
-//         dwt.enable_cycle_counter();
-
-//         // now the CYCCNT counter can't be stopped or resetted
-//         drop(dwt);
-
-//         MonoTimer {
-//             frequency: clocks.sysclk(),
-//         }
-//     }
-
-//     /// Returns the frequency at which the monotonic timer is operating at
-//     pub fn frequency(&self) -> Hertz {
-//         self.frequency
-//     }
-
-//     /// Returns an `Instant` corresponding to "now"
-//     pub fn now(&self) -> Instant {
-//         Instant {
-//             now: DWT::cycle_count(),
-//         }
-//     }
-// }
-
-/// A measurement of a monotonically nondecreasing clock
-#[derive(Clone, Copy)]
-pub struct Instant {
-    now: u32,
-}
-
-impl Instant {
-    /// Ticks elapsed since the `Instant` was created
-    pub fn elapsed(&self) -> u32 {
-        DWT::cycle_count().wrapping_sub(self.now)
-    }
-}
diff --git a/src/timer.rs b/src/timer.rs
diff --git a/src/xspi/qspi.rs b/src/xspi/qspi.rs

Original file line number	Diff line number	Diff line change
`@@ -110,7 +110,7 @@ impl<'a> Countdown<'a> {`
`110`	`110`	`}`
`111`	`111`	`}`
`112`	`112`
`113`		`-impl<'a> CountDown for Countdown<'a> {`
	`113`	`+impl CountDown for Countdown<'_> {`
`114`	`114`	`type Time = fugit::MicrosDurationU32;`
`115`	`115`
`116`	`116`	`fn start<T>(&mut self, count: T)`
Original file line number	Diff line number	Diff line change
`@@ -270,10 +270,10 @@ impl UnlockedFlashBank<'_> {`
`270`	`270`	`}`
`271`	`271`	`}`
`272`	`272`
`273`		`-impl<'a> ErrorType for UnlockedFlashBank<'a> {`
	`273`	`+impl ErrorType for UnlockedFlashBank<'_> {`
`274`	`274`	`type Error = Error;`
`275`	`275`	`}`
`276`		`-impl<'a> ReadNorFlash for UnlockedFlashBank<'a> {`
	`276`	`+impl ReadNorFlash for UnlockedFlashBank<'_> {`
`277`	`277`	`const READ_SIZE: usize = 1;`
`278`	`278`
`279`	`279`	`fn read(`
`@@ -291,7 +291,7 @@ impl<'a> ReadNorFlash for UnlockedFlashBank<'a> {`
`291`	`291`	`}`
`292`	`292`	`}`
`293`	`293`
`294`		`-impl<'a> NorFlash for UnlockedFlashBank<'a> {`
	`294`	`+impl NorFlash for UnlockedFlashBank<'_> {`
`295`	`295`	`const WRITE_SIZE: usize = super::WRITE_SIZE;`
`296`	`296`	`const ERASE_SIZE: usize = super::SECTOR_SIZE;`
`297`	`297`