Tidy nested lock calls

Author: richardeoin

examples/spi-dma-rtic.rs

@@ -141,39 +141,33 @@ mod app {
     }
 
     #[task(binds=DMA1_STR1, shared = [transfer, cs], priority=2)]
-    fn dma_complete(mut ctx: dma_complete::Context) {
+    fn dma_complete(ctx: dma_complete::Context) {
         // If desired, the transfer can scheduled again here to continue transmitting.
-        let mut cs = ctx.shared.cs;
-        ctx.shared.transfer.lock(|transfer| {
-            cs.lock(|cs| {
-                transfer.clear_transfer_complete_interrupt();
-                transfer.pause(|spi| {
-                    // At this point, the DMA transfer is done, but the data is still in the SPI output
-                    // FIFO. Wait for it to complete before disabling CS.
-                    while spi.inner().sr.read().txc().bit_is_clear() {}
-                    cs.set_high().unwrap();
-                });
+        (ctx.shared.transfer, ctx.shared.cs).lock(|transfer, cs| {
+            transfer.clear_transfer_complete_interrupt();
+            transfer.pause(|spi| {
+                // At this point, the DMA transfer is done, but the data is still in the SPI output
+                // FIFO. Wait for it to complete before disabling CS.
+                while spi.inner().sr.read().txc().bit_is_clear() {}
+                cs.set_high().unwrap();
             });
         });
     }
 
     #[idle(shared = [transfer, cs])]
-    fn idle(mut ctx: idle::Context) -> ! {
+    fn idle(ctx: idle::Context) -> ! {
         // Start the DMA transfer over SPI.
-        let mut cs = ctx.shared.cs;
-        ctx.shared.transfer.lock(|transfer| {
-            cs.lock(|cs| {
-                transfer.start(|spi| {
-                    // Set CS low for the transfer.
-                    cs.set_low().unwrap();
-
-                    // Enable TX DMA support, enable the SPI peripheral, and start the transaction.
-                    spi.enable_dma_tx();
-                    spi.inner_mut().cr1.modify(|_, w| w.spe().enabled());
-                    spi.inner_mut().cr1.modify(|_, w| w.cstart().started());
-
-                    // The transaction immediately begins as the TX FIFO is now being filled by DMA.
-                });
+        (ctx.shared.transfer, ctx.shared.cs).lock(|transfer, cs| {
+            transfer.start(|spi| {
+                // Set CS low for the transfer.
+                cs.set_low().unwrap();
+
+                // Enable TX DMA support, enable the SPI peripheral, and start the transaction.
+                spi.enable_dma_tx();
+                spi.inner_mut().cr1.modify(|_, w| w.spe().enabled());
+                spi.inner_mut().cr1.modify(|_, w| w.cstart().started());
+
+                // The transaction immediately begins as the TX FIFO is now being filled by DMA.
             });
         });