Skip to content

Commit 607ff3e

Browse files
usbalbinusbalbin
committed
fmt
1 parent dc3f15e commit 607ff3e

File tree

4 files changed

+91
-57
lines changed

4 files changed

+91
-57
lines changed

‎src/dma/bdma.rs

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -597,11 +597,17 @@ impl<I: Instance, const S: u8> InstanceStream for StreamX<I, S> {
597597
//NOTE(unsafe) Atomic write with no side-effects and we only access the bits
598598
// that belongs to the StreamX
599599
let dma = unsafe { &*I::ptr() };
600-
dma.ifcr().write(|w| w
601-
.ctcif(S).set_bit() //Clear transfer complete interrupt flag
602-
.chtif(S).set_bit() //Clear half transfer interrupt flag
603-
.cteif(S).set_bit() //Clear transfer error interrupt flag
604-
.cgif(S).set_bit() //Clear global interrupt flag
600+
dma.ifcr().write(
601+
|w| {
602+
w.ctcif(S)
603+
.set_bit() //Clear transfer complete interrupt flag
604+
.chtif(S)
605+
.set_bit() //Clear half transfer interrupt flag
606+
.cteif(S)
607+
.set_bit() //Clear transfer error interrupt flag
608+
.cgif(S)
609+
.set_bit()
610+
}, //Clear global interrupt flag
605611
);
606612
let _ = dma.isr().read();
607613
let _ = dma.isr().read(); // Delay 2 peripheral clocks

‎src/flash/mod.rs

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -277,8 +277,10 @@ const UNLOCK_KEY2: u32 = 0xCDEF_89AB;
277277

278278
#[allow(unused_unsafe)]
279279
fn unlock(bank: &BANK) {
280-
bank.keyr().write(|w| unsafe { w.key1r().bits(UNLOCK_KEY1) });
281-
bank.keyr().write(|w| unsafe { w.key1r().bits(UNLOCK_KEY2) });
280+
bank.keyr()
281+
.write(|w| unsafe { w.key1r().bits(UNLOCK_KEY1) });
282+
bank.keyr()
283+
.write(|w| unsafe { w.key1r().bits(UNLOCK_KEY2) });
282284
assert!(!bank.cr().read().lock().bit())
283285
}
284286

‎src/flash/operations.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,8 @@ impl Error {
8080
}
8181
fn clear_error_flags(regs: &BANK) {
8282
regs.ccr().write(|w| {
83-
let w = w.clr_pgserr()
83+
let w = w
84+
.clr_pgserr()
8485
.set_bit()
8586
.clr_wrperr()
8687
.set_bit()
@@ -89,9 +90,7 @@ fn clear_error_flags(regs: &BANK) {
8990
.clr_incerr();
9091

9192
#[cfg(not(feature = "rm0455"))]
92-
let w = w
93-
.set_bit()
94-
.clr_operr();
93+
let w = w.set_bit().clr_operr();
9594

9695
w.set_bit()
9796
.clr_rdperr()

‎src/sai/mod.rs

Lines changed: 73 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -186,59 +186,74 @@ pub struct Sai<SAI, INTERFACE> {
186186

187187
#[cfg(feature = "rm0455")]
188188
#[allow(clippy::upper_case_acronyms)]
189-
pub(crate) type SAI<const A: usize> = stm32h7::Periph<crate::stm32::sai1::RegisterBlock, A>;
189+
pub(crate) type SAI<const A: usize> =
190+
stm32h7::Periph<crate::stm32::sai1::RegisterBlock, A>;
190191

191192
#[cfg(not(feature = "rm0455"))]
192193
#[allow(clippy::upper_case_acronyms)]
193-
pub(crate) type SAI<const A: usize> = stm32h7::Periph<crate::stm32::sai4::RegisterBlock, A>;
194+
pub(crate) type SAI<const A: usize> =
195+
stm32h7::Periph<crate::stm32::sai4::RegisterBlock, A>;
194196

195197
// Common to all interfaces
196-
impl<INTERFACE, const A: usize> Sai<SAI<A>, INTERFACE>
197-
where SAI<A>: GetClkSAI
198+
impl<INTERFACE, const A: usize> Sai<SAI<A>, INTERFACE>
199+
where
200+
SAI<A>: GetClkSAI,
198201
{
199202
/// Low level RCC initialisation
200-
fn sai_rcc_init(&mut self, prec: <SAI<A> as GetClkSAI>::Rec)
201-
{
203+
fn sai_rcc_init(&mut self, prec: <SAI<A> as GetClkSAI>::Rec) {
202204
let _ = prec.enable().reset(); // drop, can be recreated by free method
203205
}
204206

205207
/// Access to the current master channel
206208
fn master_channel<F, T>(&self, func: F) -> T
207-
where F: FnOnce(&CH) -> T,
209+
where
210+
F: FnOnce(&CH) -> T,
208211
{
209212
func(self.rb.ch(self.master_channel as usize))
210213
}
211214

212215
/// Access to the current slave channel, if set
213216
fn slave_channel<F, T>(&self, func: F) -> Option<T>
214-
where F: FnOnce(&CH) -> T,
217+
where
218+
F: FnOnce(&CH) -> T,
215219
{
216-
self.slave_channel.map(|channel| func(self.rb.ch(channel as usize)))
220+
self.slave_channel
221+
.map(|channel| func(self.rb.ch(channel as usize)))
217222
}
218223

219224
/// Start listening for `event` on a given `channel`
220225
pub fn listen(&mut self, channel: SaiChannel, event: Event) {
221226
let ch = &self.rb.ch(channel as usize);
222227
match event {
223-
Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().set_bit()),
224-
Event::Muted => ch.im().modify(|_, w| w.mutedetie().set_bit()),
225-
Event::WrongClock => ch.im().modify(|_, w| w.wckcfgie().set_bit()),
226-
Event::Data => ch.im().modify(|_, w| w.freqie().set_bit()),
227-
Event::AnticipatedFrameSync => ch.im().modify(|_, w| w.afsdetie().set_bit()),
228-
Event::LateFrameSync => ch.im().modify(|_, w| w.lfsdetie().set_bit()),
228+
Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().set_bit()),
229+
Event::Muted => ch.im().modify(|_, w| w.mutedetie().set_bit()),
230+
Event::WrongClock => ch.im().modify(|_, w| w.wckcfgie().set_bit()),
231+
Event::Data => ch.im().modify(|_, w| w.freqie().set_bit()),
232+
Event::AnticipatedFrameSync => {
233+
ch.im().modify(|_, w| w.afsdetie().set_bit())
234+
}
235+
Event::LateFrameSync => {
236+
ch.im().modify(|_, w| w.lfsdetie().set_bit())
237+
}
229238
};
230239
}
231240

232241
/// Stop listening for `event` on a given `channel`
233242
pub fn unlisten(&mut self, channel: SaiChannel, event: Event) {
234243
let ch = &self.rb.ch(channel as usize);
235244
match event {
236-
Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().clear_bit()),
237-
Event::Muted => ch.im().modify(|_, w| w.mutedetie().clear_bit()),
238-
Event::WrongClock => ch.im().modify(|_, w| w.wckcfgie().clear_bit()),
239-
Event::Data => ch.im().modify(|_, w| w.freqie().clear_bit()),
240-
Event::AnticipatedFrameSync => ch.im().modify(|_, w| w.afsdetie().clear_bit()),
241-
Event::LateFrameSync => ch.im().modify(|_, w| w.lfsdetie().clear_bit()),
245+
Event::Overdue => ch.im().modify(|_, w| w.ovrudrie().clear_bit()),
246+
Event::Muted => ch.im().modify(|_, w| w.mutedetie().clear_bit()),
247+
Event::WrongClock => {
248+
ch.im().modify(|_, w| w.wckcfgie().clear_bit())
249+
}
250+
Event::Data => ch.im().modify(|_, w| w.freqie().clear_bit()),
251+
Event::AnticipatedFrameSync => {
252+
ch.im().modify(|_, w| w.afsdetie().clear_bit())
253+
}
254+
Event::LateFrameSync => {
255+
ch.im().modify(|_, w| w.lfsdetie().clear_bit())
256+
}
242257
};
243258
let _ = ch.im().read();
244259
let _ = ch.im().read(); // Delay 2 peripheral clocks
@@ -250,12 +265,14 @@ impl<INTERFACE, const A: usize> Sai<SAI<A>, INTERFACE>
250265
pub fn clear_irq(&mut self, channel: SaiChannel, event: Event) {
251266
let ch = &self.rb.ch(channel as usize);
252267
match event {
253-
Event::Overdue => ch.clrfr().write(|w| w.covrudr().set_bit()),
254-
Event::Muted => ch.clrfr().write(|w| w.cmutedet().set_bit()),
255-
Event::WrongClock => ch.clrfr().write(|w| w.cwckcfg().set_bit()),
256-
Event::Data => 0, // Cleared by reading/writing data
257-
Event::AnticipatedFrameSync => ch.clrfr().write(|w| w.cafsdet().set_bit()),
258-
Event::LateFrameSync => ch.clrfr().write(|w| w.clfsdet().set_bit()),
268+
Event::Overdue => ch.clrfr().write(|w| w.covrudr().set_bit()),
269+
Event::Muted => ch.clrfr().write(|w| w.cmutedet().set_bit()),
270+
Event::WrongClock => ch.clrfr().write(|w| w.cwckcfg().set_bit()),
271+
Event::Data => 0, // Cleared by reading/writing data
272+
Event::AnticipatedFrameSync => {
273+
ch.clrfr().write(|w| w.cafsdet().set_bit())
274+
}
275+
Event::LateFrameSync => ch.clrfr().write(|w| w.clfsdet().set_bit()),
259276
};
260277
let _ = ch.sr().read();
261278
let _ = ch.sr().read(); // Delay 2 peripheral clocks
@@ -274,13 +291,19 @@ impl<INTERFACE, const A: usize> Sai<SAI<A>, INTERFACE>
274291
/// Mute `channel`, this is checked at the start of each frame
275292
/// Meaningful only in Tx mode
276293
pub fn mute(&mut self, channel: SaiChannel) {
277-
self.rb.ch(channel as usize).cr2().modify(|_, w| w.mute().enabled());
294+
self.rb
295+
.ch(channel as usize)
296+
.cr2()
297+
.modify(|_, w| w.mute().enabled());
278298
}
279299

280300
/// Unmute `channel`, this is checked at the start of each frame
281301
/// Meaningful only in Tx mode
282302
pub fn unmute(&mut self, channel: SaiChannel) {
283-
self.rb.ch(channel as usize).cr2().modify(|_, w| w.mute().disabled());
303+
self.rb
304+
.ch(channel as usize)
305+
.cr2()
306+
.modify(|_, w| w.mute().disabled());
284307
}
285308

286309
/// Used to operate the audio block(s) with an external SAI for synchronization
@@ -296,42 +319,46 @@ impl<INTERFACE, const A: usize> Sai<SAI<A>, INTERFACE>
296319
/// Synchronization output for other SAI blocks
297320
pub fn set_sync_output(&mut self, channel: Option<SaiChannel>) {
298321
match channel {
299-
Some(SaiChannel::ChannelA) => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b01) ) },
300-
Some(SaiChannel::ChannelB) => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b10) ) },
301-
None => unsafe { &self.rb.gcr().modify(|_, w| w.syncout().bits(0b00) ) },
322+
Some(SaiChannel::ChannelA) => unsafe {
323+
&self.rb.gcr().modify(|_, w| w.syncout().bits(0b01))
324+
},
325+
Some(SaiChannel::ChannelB) => unsafe {
326+
&self.rb.gcr().modify(|_, w| w.syncout().bits(0b10))
327+
},
328+
None => unsafe {
329+
&self.rb.gcr().modify(|_, w| w.syncout().bits(0b00))
330+
},
302331
};
303332
}
304333

305334
/// Enable DMA for the SAI peripheral.
306335
pub fn enable_dma(&mut self, channel: SaiChannel) {
307-
self.rb.ch(channel as usize).cr1().modify(|_, w| w.dmaen().enabled());
336+
self.rb
337+
.ch(channel as usize)
338+
.cr1()
339+
.modify(|_, w| w.dmaen().enabled());
308340
}
309341

310342
/// Releases the SAI peripheral
311343
pub fn free(self) -> (SAI<A>, <SAI<A> as GetClkSAI>::Rec) {
312344
// Refer to RM0433 Rev 7 51.4.15 Disabling the SAI
313345

314346
// Master: Clear SAIEN
315-
self.master_channel(|ch| {
316-
ch.cr1().modify(|_, w| w.saien().disabled())
317-
});
347+
self.master_channel(|ch| ch.cr1().modify(|_, w| w.saien().disabled()));
318348

319349
// Master: Wait for SAI to clear at the end of the
320350
// frame
321-
while self.master_channel(|ch| {
322-
ch.cr1().read().saien().bit_is_set()
323-
}) {}
351+
while self.master_channel(|ch| ch.cr1().read().saien().bit_is_set()) {}
324352

325353
// Slave: Clear SAIEN
326-
self.slave_channel(|ch| {
327-
ch.cr1().modify(|_, w| w.saien().disabled())
328-
});
354+
self.slave_channel(|ch| ch.cr1().modify(|_, w| w.saien().disabled()));
329355

330356
// Slave: Wait for SAI to clear
331-
while self.slave_channel(|ch| {
332-
ch.cr1().read().saien().bit_is_set()
333-
}).unwrap_or(false) {}
357+
while self
358+
.slave_channel(|ch| ch.cr1().read().saien().bit_is_set())
359+
.unwrap_or(false)
360+
{}
334361

335362
(self.rb, unsafe { <SAI<A> as GetClkSAI>::Rec::new() })
336363
}
337-
}
364+
}

0 commit comments

Comments
 (0)