Fix "log" feature flag for RM0455 parts, expand CI to cover this path

Author: richardeoin

.github/workflows/ci.yml

@@ -32,8 +32,9 @@ jobs:
           - stm32h7b3
           - stm32h7b0
           - stm32h735
-    env:                        # Peripheral Feature flags
-      FLAGS: rt,xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi,defmt
+    env:
+      FLAGS: rt,defmt,log
+      PERIPHERAL: xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi
 
     steps:
       - uses: actions/checkout@v4
@@ -53,5 +54,5 @@ jobs:
         with:
           toolchain: ${{ matrix.rust }}
           targets: thumbv7em-none-eabihf
-      - run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }}
-      - run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }}
+      - run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}
+      - run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}

.github/workflows/nightly.yml

@@ -18,8 +18,9 @@ jobs:
           - log-itm
           - log-semihost
           - log-rtt
-    env:                        # Peripheral Feature flags
-      FLAGS: rt,xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi
+    env:
+      FLAGS: rt,log
+      PERIPHERAL: xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi
 
     steps:
       - uses: actions/checkout@v4
@@ -38,5 +39,5 @@ jobs:
       - uses: dtolnay/rust-toolchain@nightly
         with:
           targets: thumbv7em-none-eabihf
-      - run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ matrix.logging }}
-      - run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }}
+      - run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }},${{ matrix.logging }}
+      - run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}

src/rcc/mod.rs

@@ -985,26 +985,52 @@ impl Rcc {
                 cfgr.sws().variant().unwrap()
             );
 
-            let d1cfgr = rcc.d1cfgr.read();
-            debug!(
-                "D1CFGR register: D1CPRE={:?} HPRE={:?} D1PPRE={:?}",
-                d1cfgr.d1cpre().variant().unwrap(),
-                d1cfgr.hpre().variant().unwrap(),
-                d1cfgr.d1ppre().variant().unwrap(),
-            );
-
-            let d2cfgr = rcc.d2cfgr.read();
-            debug!(
-                "D2CFGR register: D2PPRE1={:?} D2PPRE1={:?}",
-                d2cfgr.d2ppre1().variant().unwrap(),
-                d2cfgr.d2ppre2().variant().unwrap(),
-            );
-
-            let d3cfgr = rcc.d3cfgr.read();
-            debug!(
-                "D3CFGR register: D3PPRE={:?}",
-                d3cfgr.d3ppre().variant().unwrap(),
-            );
+            #[cfg(not(feature = "rm0455"))]
+            {
+                let d1cfgr = rcc.d1cfgr.read();
+                debug!(
+                    "D1CFGR register: D1CPRE={:?} HPRE={:?} D1PPRE={:?}",
+                    d1cfgr.d1cpre().variant().unwrap(),
+                    d1cfgr.hpre().variant().unwrap(),
+                    d1cfgr.d1ppre().variant().unwrap(),
+                );
+
+                let d2cfgr = rcc.d2cfgr.read();
+                debug!(
+                    "D2CFGR register: D2PPRE1={:?} D2PPRE1={:?}",
+                    d2cfgr.d2ppre1().variant().unwrap(),
+                    d2cfgr.d2ppre2().variant().unwrap(),
+                );
+
+                let d3cfgr = rcc.d3cfgr.read();
+                debug!(
+                    "D3CFGR register: D3PPRE={:?}",
+                    d3cfgr.d3ppre().variant().unwrap(),
+                );
+            }
+            #[cfg(feature = "rm0455")]
+            {
+                let cdcfgr1 = rcc.cdcfgr1.read();
+                debug!(
+                    "CDCFGR1 register: CDCPRE={:?} HPRE={:?} CDPPRE={:?}",
+                    cdcfgr1.cdcpre().variant().unwrap(),
+                    cdcfgr1.hpre().variant().unwrap(),
+                    cdcfgr1.cdppre().variant().unwrap(),
+                );
+
+                let cdcfgr2 = rcc.cdcfgr2.read();
+                debug!(
+                    "CDCFGR2 register: CDPPRE1={:?} CDPPRE1={:?}",
+                    cdcfgr2.cdppre1().variant().unwrap(),
+                    cdcfgr2.cdppre2().variant().unwrap(),
+                );
+
+                let srdcfgr = rcc.srdcfgr.read();
+                debug!(
+                    "SRDCFGR register: SRDPPRE={:?}",
+                    srdcfgr.srdppre().bits(),
+                );
+            }
 
             let pllckselr = rcc.pllckselr.read();
             debug!(