|
| 1 | +#![no_main] |
| 2 | +#![no_std] |
| 3 | + |
| 4 | +use cortex_m_rt::entry; |
| 5 | +#[macro_use] |
| 6 | +mod utilities; |
| 7 | +use log::info; |
| 8 | + |
| 9 | +use stm32h7xx_hal::{pac, prelude::*, serial::config::Config}; |
| 10 | + |
| 11 | +use core::fmt::Write; |
| 12 | + |
| 13 | +#[entry] |
| 14 | +fn main() -> ! { |
| 15 | + utilities::logger::init(); |
| 16 | + let dp = pac::Peripherals::take().unwrap(); |
| 17 | + |
| 18 | + // Constrain and Freeze power |
| 19 | + info!("Setup PWR... "); |
| 20 | + let pwr = dp.PWR.constrain(); |
| 21 | + let pwrcfg = example_power!(pwr).freeze(); |
| 22 | + |
| 23 | + // Constrain and Freeze clock |
| 24 | + info!("Setup RCC... "); |
| 25 | + let rcc = dp.RCC.constrain(); |
| 26 | + let ccdr = rcc.sys_ck(160.mhz()).freeze(pwrcfg, &dp.SYSCFG); |
| 27 | + |
| 28 | + // Acquire the GPIOC peripheral. This also enables the clock for |
| 29 | + // GPIOC in the RCC register. |
| 30 | + let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC); |
| 31 | + |
| 32 | + let tx = gpioc.pc10.into_alternate_af7(); |
| 33 | + let rx = gpioc.pc11.into_alternate_af7(); |
| 34 | + let clk = gpioc.pc12.into_alternate_af7(); |
| 35 | + |
| 36 | + info!(""); |
| 37 | + info!("stm32h7xx-hal example - USART Advanced"); |
| 38 | + info!(""); |
| 39 | + |
| 40 | + // Configure the serial peripheral in synchronous mode |
| 41 | + let config = Config::new(115_200.bps()).lastbitclockpulse(true); |
| 42 | + let serial = dp |
| 43 | + .USART3 |
| 44 | + .serial((tx, rx, clk), config, ccdr.peripheral.USART3, &ccdr.clocks) |
| 45 | + .unwrap(); |
| 46 | + |
| 47 | + let (mut tx, _rx) = serial.split(); |
| 48 | + |
| 49 | + loop { |
| 50 | + // core::fmt::Write is implemented for tx. |
| 51 | + writeln!(tx, "Hello, world!").unwrap(); |
| 52 | + } |
| 53 | +} |
0 commit comments