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BryanKadzbaneldruin
BryanKadzban
authored and
eldruin
committed
Run rustfmt on rcc.rs
"cargo fmt" does not work because it requires both test mode and the #![no_std] attribute, which the crate lib.rs doesn't enable in test mode. But manually running rustfmt does.
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‎src/rcc.rs

Lines changed: 67 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -616,45 +616,61 @@ impl CFGR {
616616
// the software division. Fortunately our 26 bit choice for the
617617
// decimal place, and the fact that these are 1/N, means we can
618618
// fit them into 26 bits, so a u32 is fine.
619-
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
620-
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllp {
621-
PLLP::Div2 => 2u32,
622-
PLLP::Div4 => 4u32,
623-
PLLP::Div6 => 6u32,
624-
PLLP::Div8 => 8u32,
625-
} + 1) >> 1;
626-
sysclk =
627-
(((base_clk as u64 * self.plln as u64 * one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
628-
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
619+
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
620+
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
621+
/ match self.pllp {
622+
PLLP::Div2 => 2u32,
623+
PLLP::Div4 => 4u32,
624+
PLLP::Div6 => 6u32,
625+
PLLP::Div8 => 8u32,
626+
}
627+
+ 1)
628+
>> 1;
629+
sysclk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
630+
>> Self::FIXED_POINT_RSHIFT)
631+
* one_over_p as u64)
632+
>> Self::FIXED_POINT_RSHIFT
633+
<< Self::BASE_CLK_SHIFT;
629634
}
630635

631636
// Check if pll48clk is valid
632637
if let Some(pll48clk) = self.pll48clk {
633638
match pll48clk {
634639
PLL48CLK::Pllq => {
635640
pll48clk_valid = {
636-
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
637-
let one_over_q = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1;
638-
let pll48clk = (((base_clk as u64 * self.plln as u64
639-
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
640-
* one_over_q as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
641+
let one_over_m =
642+
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
643+
let one_over_q =
644+
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1;
645+
let pll48clk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
646+
>> Self::FIXED_POINT_RSHIFT)
647+
* one_over_q as u64)
648+
>> Self::FIXED_POINT_RSHIFT
649+
<< Self::BASE_CLK_SHIFT;
641650
(48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk)
642651
}
643652
}
644653
PLL48CLK::Pllsai => {
645654
pll48clk_valid = {
646655
if self.use_pllsai {
647656
// base_clk * pllsain has the same range as above
648-
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
649-
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllsaip {
650-
PLLSAIP::Div2 => 2u32,
651-
PLLSAIP::Div4 => 4u32,
652-
PLLSAIP::Div6 => 6u32,
653-
PLLSAIP::Div8 => 8u32,
654-
} + 1) >> 1;
655-
let pll48clk = (((base_clk as u64 * self.pllsain as u64
656-
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
657-
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
657+
let one_over_m =
658+
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
659+
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
660+
/ match self.pllsaip {
661+
PLLSAIP::Div2 => 2u32,
662+
PLLSAIP::Div4 => 4u32,
663+
PLLSAIP::Div6 => 6u32,
664+
PLLSAIP::Div8 => 8u32,
665+
}
666+
+ 1)
667+
>> 1;
668+
let pll48clk =
669+
(((base_clk as u64 * self.pllsain as u64 * one_over_m as u64)
670+
>> Self::FIXED_POINT_RSHIFT)
671+
* one_over_p as u64)
672+
>> Self::FIXED_POINT_RSHIFT
673+
<< Self::BASE_CLK_SHIFT;
658674
(48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk)
659675
} else {
660676
false
@@ -850,9 +866,12 @@ impl CFGR {
850866
continue;
851867
}
852868
// See the comments around Self::FIXED_POINT_LSHIFT to see how this works.
853-
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;
854-
let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT) * n as u64
855-
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT) as u32;
869+
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;
870+
let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT)
871+
* n as u64
872+
* one_over_m as u64)
873+
>> Self::FIXED_POINT_RSHIFT
874+
<< Self::BASE_CLK_SHIFT) as u32;
856875
if f_vco_clock < 50_000_000 {
857876
m += 1;
858877
n = 432;
@@ -908,7 +927,8 @@ impl CFGR {
908927
Some(hse) => hse.freq,
909928
None => HSI_FREQUENCY,
910929
}
911-
.raw() >> Self::BASE_CLK_SHIFT;
930+
.raw()
931+
>> Self::BASE_CLK_SHIFT;
912932

913933
let sysclk = if let Some(clk) = self.sysclk {
914934
clk
@@ -936,21 +956,29 @@ impl CFGR {
936956

937957
// We check if (pllm, plln, pllp) allow to obtain the requested Sysclk,
938958
// so that we don't have to calculate them
939-
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
940-
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllp {
941-
PLLP::Div2 => 2u32,
942-
PLLP::Div4 => 4u32,
943-
PLLP::Div6 => 6u32,
944-
PLLP::Div8 => 8u32,
945-
} + 1) >> 1;
959+
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
960+
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
961+
/ match self.pllp {
962+
PLLP::Div2 => 2u32,
963+
PLLP::Div4 => 4u32,
964+
PLLP::Div6 => 6u32,
965+
PLLP::Div8 => 8u32,
966+
}
967+
+ 1)
968+
>> 1;
946969
let p_ok = (sysclk as u64)
947-
== (((base_clk as u64 * self.plln as u64 * one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
948-
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
970+
== (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
971+
>> Self::FIXED_POINT_RSHIFT)
972+
* one_over_p as u64)
973+
>> Self::FIXED_POINT_RSHIFT
974+
<< Self::BASE_CLK_SHIFT;
949975
if p_ok && q.is_none() {
950976
return;
951977
}
952978

953-
if let Some((m, n, p, q)) = CFGR::calculate_mnpq(base_clk << Self::BASE_CLK_SHIFT, FreqRequest { p, q }) {
979+
if let Some((m, n, p, q)) =
980+
CFGR::calculate_mnpq(base_clk << Self::BASE_CLK_SHIFT, FreqRequest { p, q })
981+
{
954982
self.pllm = m as u8;
955983
self.plln = n as u16;
956984
if let Some(p) = p {

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