diff --git a/CHANGELOG.md b/CHANGELOG.md
index 574dd973..647e6005 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -42,6 +42,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - example of using i2s in out with rtic and interrupt.
 - example of using USB CDC with interrupts.
 - Added non-blocking I2C based on DMA [#534]
+- Capability to release and reuse SPI peripheral after using it with DMA.
 
 [#481]: https://github.com/stm32-rs/stm32f4xx-hal/pull/481
 [#489]: https://github.com/stm32-rs/stm32f4xx-hal/pull/489
diff --git a/Cargo.toml b/Cargo.toml
index a09e1de4..2432938e 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -47,6 +47,7 @@ rtic-monotonic = { version = "1.0", optional = true }
 systick-monotonic = { version = "1.0", optional = true }
 bitflags = "1.3.2"
 embedded-storage = "0.2"
+paste = "1.0.9"
 
 [dependencies.time]
 version = "0.3.14"
diff --git a/examples/spi_dma.rs b/examples/spi_dma.rs
index 3d5d8921..c1b3ed8e 100644
--- a/examples/spi_dma.rs
+++ b/examples/spi_dma.rs
@@ -11,6 +11,7 @@ use embedded_hal::spi::{Mode, Phase, Polarity};
 use stm32f4xx_hal::pac::interrupt;
 use stm32f4xx_hal::{
     dma::{config, traits::StreamISR, MemoryToPeripheral, Stream4, StreamsTuple, Transfer},
+    gpio::{PB13, PB15},
     pac,
     prelude::*,
     spi::*,
@@ -21,7 +22,7 @@ const ARRAY_SIZE: usize = 100;
 type SpiDma = Transfer<
     Stream4<pac::DMA1>,
     0,
-    Tx<pac::SPI2>,
+    Tx<pac::SPI2, (PB13, NoMiso, PB15), false, Master>,
     MemoryToPeripheral,
     &'static mut [u8; ARRAY_SIZE],
 >;
@@ -39,8 +40,8 @@ fn main() -> ! {
         let stream = steams.4;
 
         let gpiob = dp.GPIOB.split();
-        let pb15 = gpiob.pb15.into_alternate().internal_pull_up(true);
-        let pb13 = gpiob.pb13.into_alternate();
+        let pb15 = gpiob.pb15.internal_pull_up(true);
+        let pb13 = gpiob.pb13;
 
         let mode = Mode {
             polarity: Polarity::IdleLow,
diff --git a/src/dma/traits.rs b/src/dma/traits.rs
index c46432d8..c9d2fda9 100644
--- a/src/dma/traits.rs
+++ b/src/dma/traits.rs
@@ -6,6 +6,7 @@ use crate::{
     serial, spi, timer,
 };
 use core::ops::Deref;
+use paste::paste;
 
 pub(crate) mod sealed {
     /// Converts value to bits for setting a register value.
@@ -284,6 +285,20 @@ macro_rules! dma_map {
     };
 }
 
+macro_rules! dma_spi_map {
+    ($(($Stream:ty, $C:literal, $RxTx:ident, $Peripheral:ty, $Dir:ty)),+ $(,)*) => {
+        $(
+            unsafe impl<PINS, const BIDI: bool, OPERATION>
+            DMASet<$Stream, $C, $Dir> for spi::$RxTx<$Peripheral, PINS, BIDI, OPERATION> {}
+
+            paste! {
+                unsafe impl<PINS, const BIDI: bool, OPERATION>
+                DMASet<$Stream, $C, $Dir> for spi::[<$RxTx Coupled>]<$Peripheral, PINS, BIDI, OPERATION> {}
+            }
+        )+
+    };
+}
+
 #[cfg(any(
     feature = "stm32f401",
     feature = "stm32f417",
@@ -330,15 +345,36 @@ dma_map!(
     (Stream7<DMA1>, 5, timer::CCR3<pac::TIM3>, MemoryToPeripheral), //TIM3_CH3
     (Stream7<DMA1>, 5, timer::CCR3<pac::TIM3>, PeripheralToMemory), //TIM3_CH3
     (Stream0<DMA1>, 0, pac::SPI3, PeripheralToMemory),       //SPI3_RX
-    (Stream0<DMA1>, 0, spi::Rx<pac::SPI3>, PeripheralToMemory), //SPI3_RX
     (Stream2<DMA1>, 0, pac::SPI3, PeripheralToMemory),       //SPI3_RX
-    (Stream2<DMA1>, 0, spi::Rx<pac::SPI3>, PeripheralToMemory), //SPI3_RX
     (Stream4<DMA1>, 3, pac::I2C3, MemoryToPeripheral),       //I2C3_TX
     (Stream4<DMA1>, 3, i2c::Tx<pac::I2C3>, MemoryToPeripheral),       //I2C3_TX
     (Stream5<DMA1>, 0, pac::SPI3, MemoryToPeripheral),       //SPI3_TX
-    (Stream5<DMA1>, 0, spi::Tx<pac::SPI3>, MemoryToPeripheral), //SPI3_TX
     (Stream7<DMA1>, 0, pac::SPI3, MemoryToPeripheral),       //SPI3_TX
-    (Stream7<DMA1>, 0, spi::Tx<pac::SPI3>, MemoryToPeripheral), //SPI3_TX
+);
+
+#[cfg(any(
+    feature = "stm32f401",
+    feature = "stm32f417",
+    feature = "stm32f415",
+    feature = "stm32f405",
+    feature = "stm32f407",
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f446",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream0<DMA1>, 0, Rx, pac::SPI3, PeripheralToMemory), //SPI3_RX
+    (Stream2<DMA1>, 0, Rx, pac::SPI3, PeripheralToMemory), //SPI3_RX
+    (Stream5<DMA1>, 0, Tx, pac::SPI3, MemoryToPeripheral), //SPI3_TX
+    (Stream7<DMA1>, 0, Tx, pac::SPI3, MemoryToPeripheral), //SPI3_TX
 );
 
 #[cfg(any(
@@ -437,11 +473,9 @@ dma_map!(
     (Stream2<DMA1>, 7, pac::I2C2, PeripheralToMemory),              //I2C2_RX
     (Stream2<DMA1>, 7, i2c::Rx<pac::I2C2>, PeripheralToMemory),     //I2C2_RX
     (Stream3<DMA1>, 0, pac::SPI2, PeripheralToMemory),       //SPI2_RX
-    (Stream3<DMA1>, 0, spi::Rx<pac::SPI2>, PeripheralToMemory), //SPI2_RX
     (Stream3<DMA1>, 7, pac::I2C2, PeripheralToMemory),          //I2C2_RX
-    (Stream3<DMA1>, 7, spi::Rx<pac::I2C2>, PeripheralToMemory), //I2C2_RX
+    (Stream3<DMA1>, 7, i2c::Rx<pac::I2C2>, PeripheralToMemory), //I2C2_RX
     (Stream4<DMA1>, 0, pac::SPI2, MemoryToPeripheral),       //SPI2_TX
-    (Stream4<DMA1>, 0, spi::Tx<pac::SPI2>, MemoryToPeripheral), // SPI2_TX
     (Stream5<DMA1>, 1, pac::I2C1, PeripheralToMemory),          //I2C1_RX
     (Stream5<DMA1>, 1, i2c::Rx<pac::I2C1>, PeripheralToMemory), //I2C1_RX
     (Stream5<DMA1>, 4, pac::USART2, PeripheralToMemory),     //USART2_RX
@@ -453,11 +487,9 @@ dma_map!(
     (Stream0<DMA2>, 0, pac::ADC1, PeripheralToMemory),       //ADC1
     (Stream0<DMA2>, 0, Adc<pac::ADC1>, PeripheralToMemory),
     (Stream0<DMA2>, 3, pac::SPI1, PeripheralToMemory), //SPI1_RX
-    (Stream0<DMA2>, 3, spi::Rx<pac::SPI1>, PeripheralToMemory), //SPI1_RX
     (Stream1<DMA2>, 5, pac::USART6, PeripheralToMemory), //USART6_RX
     (Stream1<DMA2>, 5, serial::Rx<pac::USART6>, PeripheralToMemory), //USART6_RX
     (Stream2<DMA2>, 3, pac::SPI1, PeripheralToMemory), //SPI1_RX
-    (Stream2<DMA2>, 3, spi::Rx<pac::SPI1>, PeripheralToMemory), //SPI1_RX
     (Stream2<DMA2>, 4, pac::USART1, PeripheralToMemory), //USART1_RX
     (Stream2<DMA2>, 4, serial::Rx<pac::USART1>, PeripheralToMemory), //USART1_RX
     (Stream2<DMA2>, 5, pac::USART6, PeripheralToMemory), //USART6_RX
@@ -497,6 +529,32 @@ dma_map!(
     (Stream7<DMA2>, 0, MemoryToMemory<u32>, MemoryToMemory<u32>),
 );
 
+#[cfg(any(
+    feature = "stm32f401",
+    feature = "stm32f417",
+    feature = "stm32f415",
+    feature = "stm32f405",
+    feature = "stm32f407",
+    feature = "stm32f410",
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f446",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream3<DMA1>, 0, Rx, pac::SPI2, PeripheralToMemory), //SPI2_RX
+    (Stream4<DMA1>, 0, Tx, pac::SPI2, MemoryToPeripheral), // SPI2_TX
+    (Stream0<DMA2>, 3, Rx, pac::SPI1, PeripheralToMemory), //SPI1_RX
+    (Stream2<DMA2>, 3, Rx, pac::SPI1, PeripheralToMemory), //SPI1_RX
+);
+
 #[cfg(any(
     feature = "stm32f401",
     feature = "stm32f417",
@@ -586,9 +644,26 @@ dma_map!(
     (Stream7<DMA1>, 1, pac::I2C1, MemoryToPeripheral),          //I2C1_TX
     (Stream7<DMA1>, 1, i2c::Tx<pac::I2C1>, MemoryToPeripheral), //I2C1_TX
     (Stream3<DMA2>, 3, pac::SPI1, MemoryToPeripheral), //SPI1_TX
-    (Stream3<DMA2>, 3, spi::Tx<pac::SPI1>, MemoryToPeripheral), //SPI1_TX
     (Stream5<DMA2>, 3, pac::SPI1, MemoryToPeripheral), //SPI1_TX
-    (Stream5<DMA2>, 3, spi::Tx<pac::SPI1>, MemoryToPeripheral), //SPI1_TX
+);
+
+#[cfg(any(
+    feature = "stm32f401",
+    feature = "stm32f417",
+    feature = "stm32f415",
+    feature = "stm32f405",
+    feature = "stm32f407",
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f446",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream3<DMA2>, 3, Tx, pac::SPI1, MemoryToPeripheral), //SPI1_TX
+    (Stream5<DMA2>, 3, Tx, pac::SPI1, MemoryToPeripheral), //SPI1_TX
 );
 
 #[cfg(any(
@@ -607,13 +682,30 @@ dma_map!(
 ))]
 dma_map!(
     (Stream0<DMA2>, 4, pac::SPI4, PeripheralToMemory), //SPI4_RX
-    (Stream0<DMA2>, 4, spi::Rx<pac::SPI4>, PeripheralToMemory), //SPI4_RX
     (Stream1<DMA2>, 4, pac::SPI4, MemoryToPeripheral), //SPI4_TX
-    (Stream1<DMA2>, 4, spi::Tx<pac::SPI4>, MemoryToPeripheral), //SPI4_TX
     (Stream3<DMA2>, 5, pac::SPI4, PeripheralToMemory), //SPI4_RX:DMA_CHANNEL_5
-    (Stream3<DMA2>, 5, spi::Rx<pac::SPI4>, PeripheralToMemory), //SPI4_RX:DMA_CHANNEL_5
     (Stream4<DMA2>, 5, pac::SPI4, MemoryToPeripheral), //SPI4_TX:DMA_CHANNEL_5
-    (Stream4<DMA2>, 5, spi::Tx<pac::SPI4>, MemoryToPeripheral), //SPI4_TX:DMA_CHANNEL_5
+);
+
+#[cfg(any(
+    feature = "stm32f401",
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f446",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream0<DMA2>, 4, Rx, pac::SPI4, PeripheralToMemory), //SPI4_RX
+    (Stream1<DMA2>, 4, Tx, pac::SPI4, MemoryToPeripheral), //SPI4_TX
+    (Stream3<DMA2>, 5, Rx, pac::SPI4, PeripheralToMemory), //SPI4_RX:DMA_CHANNEL_5
+    (Stream4<DMA2>, 5, Tx, pac::SPI4, MemoryToPeripheral), //SPI4_TX:DMA_CHANNEL_5
 );
 
 #[cfg(any(
@@ -936,13 +1028,23 @@ dma_map!(
     (Stream7<DMA1>, 1, i2c::Tx<pac::I2C1>, MemoryToPeripheral), //I2C1_TX:DMA_CHANNEL_1
     (Stream7<DMA1>, 6, pac::USART2, PeripheralToMemory), //USART2_RX:DMA_CHANNEL_6
     (Stream2<DMA2>, 2, pac::SPI1, MemoryToPeripheral), //SPI1_TX
-    (Stream2<DMA2>, 2, spi::Tx<pac::SPI1>, MemoryToPeripheral), //SPI1_TX
     (Stream3<DMA2>, 3, pac::SPI1, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
-    (Stream3<DMA2>, 3, spi::Tx<pac::SPI1>, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
     (Stream5<DMA2>, 3, pac::SPI1, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
-    (Stream5<DMA2>, 3, spi::Tx<pac::SPI1>, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
     (Stream5<DMA2>, 5, pac::SPI5, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_5
-    (Stream5<DMA2>, 5, spi::Tx<pac::SPI5>, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_5
+);
+
+#[cfg(any(
+    feature = "stm32f410",
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+))]
+dma_spi_map!(
+    (Stream2<DMA2>, 2, Tx, pac::SPI1, MemoryToPeripheral), //SPI1_TX
+    (Stream3<DMA2>, 3, Tx, pac::SPI1, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
+    (Stream5<DMA2>, 3, Tx, pac::SPI1, MemoryToPeripheral), //SPI1_TX:DMA_CHANNEL_3
+    (Stream5<DMA2>, 5, Tx, pac::SPI5, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_5
 );
 
 #[cfg(any(
@@ -960,13 +1062,29 @@ dma_map!(
 ))]
 dma_map!(
     (Stream3<DMA2>, 2, pac::SPI5, PeripheralToMemory), //SPI5_RX
-    (Stream3<DMA2>, 2, spi::Rx<pac::SPI5>, PeripheralToMemory), //SPI5_RX
     (Stream4<DMA2>, 2, pac::SPI5, MemoryToPeripheral), //SPI5_TX
-    (Stream4<DMA2>, 2, spi::Tx<pac::SPI5>, MemoryToPeripheral), //SPI5_TX
     (Stream5<DMA2>, 7, pac::SPI5, PeripheralToMemory), //SPI5_RX:DMA_CHANNEL_7
-    (Stream5<DMA2>, 7, spi::Rx<pac::SPI5>, PeripheralToMemory), //SPI5_RX:DMA_CHANNEL_7
     (Stream6<DMA2>, 7, pac::SPI5, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_7
-    (Stream6<DMA2>, 7, spi::Tx<pac::SPI5>, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_7
+);
+
+#[cfg(any(
+    feature = "stm32f410",
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream3<DMA2>, 2, Rx, pac::SPI5, PeripheralToMemory), //SPI5_RX
+    (Stream4<DMA2>, 2, Tx, pac::SPI5, MemoryToPeripheral), //SPI5_TX
+    (Stream5<DMA2>, 7, Rx, pac::SPI5, PeripheralToMemory), //SPI5_RX:DMA_CHANNEL_7
+    (Stream6<DMA2>, 7, Tx, pac::SPI5, MemoryToPeripheral), //SPI5_TX:DMA_CHANNEL_7
 );
 
 #[cfg(any(
@@ -992,8 +1110,17 @@ address!((pac::SPI5, dr, u8),);
 ))]
 dma_map!(
     (Stream4<DMA2>, 4, pac::SPI4, PeripheralToMemory), //SPI4_RX);
-    (Stream4<DMA2>, 4, spi::Rx<pac::SPI4>, PeripheralToMemory),
-); //SPI4_RX);
+);
+
+#[cfg(any(
+    feature = "stm32f411",
+    feature = "stm32f412",
+    feature = "stm32f413",
+    feature = "stm32f423",
+))]
+dma_spi_map!(
+    (Stream4<DMA2>, 4, Rx, pac::SPI4, PeripheralToMemory), // SPI4_RX
+);
 
 /* TODO: DFSDM support
 #[cfg(feature = "stm32f412")]
@@ -1147,9 +1274,20 @@ address!(
 ))]
 dma_map!(
     (Stream5<DMA2>, 1, pac::SPI6, MemoryToPeripheral), //SPI6_TX
-    (Stream5<DMA2>, 1, spi::Tx<pac::SPI6>, MemoryToPeripheral), //SPI6_TX
     (Stream6<DMA2>, 1, pac::SPI6, PeripheralToMemory), //SPI6_RX
-    (Stream6<DMA2>, 1, spi::Rx<pac::SPI6>, PeripheralToMemory), //SPI6_RX
+);
+
+#[cfg(any(
+    feature = "stm32f427",
+    feature = "stm32f439",
+    feature = "stm32f437",
+    feature = "stm32f429",
+    feature = "stm32f469",
+    feature = "stm32f479",
+))]
+dma_spi_map!(
+    (Stream5<DMA2>, 1, Tx, pac::SPI6, MemoryToPeripheral), //SPI6_TX
+    (Stream6<DMA2>, 1, Rx, pac::SPI6, PeripheralToMemory), //SPI6_RX
 );
 
 #[cfg(any(
diff --git a/src/spi.rs b/src/spi.rs
index db67824b..17bc09c1 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -681,49 +681,118 @@ impl<SPI: Instance, PINS, const BIDI: bool, W: FrameSize, OPERATION>
 
 // Spi DMA
 
-impl<SPI: Instance, PINS, const BIDI: bool> Spi<SPI, PINS, BIDI, u8, Master> {
-    pub fn use_dma(self) -> DmaBuilder<SPI> {
-        DmaBuilder { spi: self.spi }
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> Spi<SPI, PINS, BIDI, u8, OPERATION> {
+    pub fn use_dma(self) -> DmaBuilder<SPI, PINS, BIDI, OPERATION> {
+        DmaBuilder { spi: self }
     }
 }
 
-pub struct DmaBuilder<SPI> {
-    spi: SPI,
+pub struct DmaBuilder<SPI: Instance, PINS, const BIDI: bool, OPERATION> {
+    spi: Spi<SPI, PINS, BIDI, u8, OPERATION>,
+}
+
+pub struct Tx<SPI: Instance, PINS, const BIDI: bool, OPERATION> {
+    spi: Spi<SPI, PINS, BIDI, u8, OPERATION>,
+}
+
+pub struct Rx<SPI: Instance, PINS, const BIDI: bool, OPERATION> {
+    spi: Spi<SPI, PINS, BIDI, u8, OPERATION>,
+}
+
+pub struct TxCoupled<SPI: Instance, PINS, const BIDI: bool, OPERATION> {
+    spi: Spi<SPI, PINS, BIDI, u8, OPERATION>,
+}
+
+pub struct RxCoupled<SPI: Instance, PINS, const BIDI: bool, OPERATION> {
+    spi: PhantomData<Spi<SPI, PINS, BIDI, u8, OPERATION>>,
 }
 
-pub struct Tx<SPI> {
-    spi: PhantomData<SPI>,
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> DmaBuilder<SPI, PINS, BIDI, OPERATION> {
+    pub fn tx(self) -> Tx<SPI, PINS, BIDI, OPERATION> {
+        self.spi.spi.cr2.modify(|_, w| w.txdmaen().enabled());
+        Tx { spi: self.spi }
+    }
+
+    pub fn rx(self) -> Rx<SPI, PINS, BIDI, OPERATION> {
+        self.spi.spi.cr2.modify(|_, w| w.rxdmaen().enabled());
+        Rx { spi: self.spi }
+    }
+
+    pub fn txrx(
+        self,
+    ) -> (
+        TxCoupled<SPI, PINS, BIDI, OPERATION>,
+        RxCoupled<SPI, PINS, BIDI, OPERATION>,
+    ) {
+        self.spi
+            .spi
+            .cr2
+            .modify(|_, w| w.txdmaen().enabled().rxdmaen().enabled());
+        (TxCoupled { spi: self.spi }, RxCoupled { spi: PhantomData })
+    }
 }
 
-pub struct Rx<SPI> {
-    spi: PhantomData<SPI>,
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> Rx<SPI, PINS, BIDI, OPERATION> {
+    pub fn release(self) -> Spi<SPI, PINS, BIDI, u8, OPERATION> {
+        self.spi.spi.cr2.modify(|_, w| w.rxdmaen().disabled());
+        self.spi
+    }
 }
 
-impl<SPI: Instance> DmaBuilder<SPI> {
-    pub fn tx(self) -> Tx<SPI> {
-        self.new_tx()
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> Tx<SPI, PINS, BIDI, OPERATION> {
+    pub fn release(self) -> Spi<SPI, PINS, BIDI, u8, OPERATION> {
+        self.spi.spi.cr2.modify(|_, w| w.txdmaen().disabled());
+        self.spi
     }
+}
 
-    pub fn rx(self) -> Rx<SPI> {
-        self.new_rx()
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> TxCoupled<SPI, PINS, BIDI, OPERATION> {
+    pub fn release(
+        self,
+        _couple: RxCoupled<SPI, PINS, BIDI, OPERATION>,
+    ) -> Spi<SPI, PINS, BIDI, u8, OPERATION> {
+        self.spi
+            .spi
+            .cr2
+            .modify(|_, w| w.rxdmaen().disabled().txdmaen().disabled());
+        self.spi
     }
+}
 
-    pub fn txrx(self) -> (Tx<SPI>, Rx<SPI>) {
-        (self.new_tx(), self.new_rx())
+impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> RxCoupled<SPI, PINS, BIDI, OPERATION> {
+    pub fn release(
+        self,
+        couple: TxCoupled<SPI, PINS, BIDI, OPERATION>,
+    ) -> Spi<SPI, PINS, BIDI, u8, OPERATION> {
+        couple.release(self)
     }
+}
 
-    fn new_tx(&self) -> Tx<SPI> {
-        self.spi.cr2.modify(|_, w| w.txdmaen().enabled());
-        Tx { spi: PhantomData }
+unsafe impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> PeriAddress
+    for Rx<SPI, PINS, BIDI, OPERATION>
+{
+    #[inline(always)]
+    fn address(&self) -> u32 {
+        unsafe { &(*SPI::ptr()).dr as *const _ as u32 }
     }
 
-    fn new_rx(self) -> Rx<SPI> {
-        self.spi.cr2.modify(|_, w| w.rxdmaen().enabled());
-        Rx { spi: PhantomData }
+    type MemSize = u8;
+}
+
+unsafe impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> PeriAddress
+    for Tx<SPI, PINS, BIDI, OPERATION>
+{
+    #[inline(always)]
+    fn address(&self) -> u32 {
+        unsafe { &(*SPI::ptr()).dr as *const _ as u32 }
     }
+
+    type MemSize = u8;
 }
 
-unsafe impl<SPI: Instance> PeriAddress for Rx<SPI> {
+unsafe impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> PeriAddress
+    for RxCoupled<SPI, PINS, BIDI, OPERATION>
+{
     #[inline(always)]
     fn address(&self) -> u32 {
         unsafe { &(*SPI::ptr()).dr as *const _ as u32 }
@@ -732,7 +801,9 @@ unsafe impl<SPI: Instance> PeriAddress for Rx<SPI> {
     type MemSize = u8;
 }
 
-unsafe impl<SPI: Instance> PeriAddress for Tx<SPI> {
+unsafe impl<SPI: Instance, PINS, const BIDI: bool, OPERATION> PeriAddress
+    for TxCoupled<SPI, PINS, BIDI, OPERATION>
+{
     #[inline(always)]
     fn address(&self) -> u32 {
         unsafe { &(*SPI::ptr()).dr as *const _ as u32 }