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burrbullburrbull
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Merge pull request #825 from stm32-rs/update-write
update PACs
2 parents f3e5246 + ece7fae commit ed88ea1

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14 files changed

+61
-57
lines changed

14 files changed

+61
-57
lines changed

‎CHANGELOG.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
77

88
## [Unreleased]
99

10+
- Bump `stm32f4-staging`
11+
1012
## [v0.22.1] - 2024-11-03
1113

1214
- Fix pac `defmt` feature

‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ micromath = { version = "2.1.0", optional = true }
6767

6868
[dependencies.stm32f4]
6969
package = "stm32f4-staging"
70-
version = "0.16.1"
70+
version = "0.17.0"
7171
features = ["atomics"]
7272

7373
[dependencies.time]

‎src/adc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -484,7 +484,7 @@ macro_rules! adc {
484484
config::Sequence::Fourteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq14().bits(channel) }),
485485
config::Sequence::Fifteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq15().bits(channel) }),
486486
config::Sequence::Sixteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq16().bits(channel) }),
487-
}
487+
};
488488

489489
fn replace_bits(mut v: u32, offset: u32, width: u32, value: u32) -> u32 {
490490
let mask = !(((1 << width) -1) << (offset * width));
@@ -500,7 +500,7 @@ macro_rules! adc {
500500
0..=9 => self.adc_reg.smpr2().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch, 3, st)) }),
501501
10..=18 => self.adc_reg.smpr1().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch-10, 3, st)) }),
502502
_ => unimplemented!(),
503-
}
503+
};
504504
}
505505

506506
/// Returns the current sample stored in the ADC data register

‎src/dsi.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -387,7 +387,7 @@ impl DsiHost {
387387
.modify(|_, w| unsafe { w.cmdsize().bits(display_config.active_width) });
388388

389389
// Tearing effect acknowledge request
390-
dsi.cmcr().modify(|_, w| w.teare().set_bit())
390+
dsi.cmcr().modify(|_, w| w.teare().set_bit());
391391
}
392392
}
393393

‎src/fsmc_lcd/mod.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ fn configure_bcr1<WORD: Word>(bcr: &fsmc::BCR1) {
302302
w.muxen().disabled();
303303
// Enable this memory bank
304304
w.mbken().enabled()
305-
})
305+
});
306306
}
307307

308308
/// Configures an SRAM/NOR-Flash chip-select control register for LCD interface use
@@ -354,7 +354,7 @@ fn configure_bcr(bcr: &fsmc::BCR) {
354354
// Enable this memory bank
355355
.mbken()
356356
.enabled()
357-
})
357+
});
358358
}
359359

360360
/// Configures a read timing register
@@ -370,7 +370,7 @@ fn configure_btr(btr: &fsmc::BTR, read_timing: &Timing) {
370370
.bits(read_timing.address_hold)
371371
.addset()
372372
.bits(read_timing.address_setup)
373-
})
373+
});
374374
}
375375
/// Configures a write timing register
376376
fn configure_bwtr(bwtr: &fsmc::BWTR, write_timing: &Timing) {
@@ -385,7 +385,7 @@ fn configure_bwtr(bwtr: &fsmc::BWTR, write_timing: &Timing) {
385385
.bits(write_timing.address_hold)
386386
.addset()
387387
.bits(write_timing.address_setup)
388-
})
388+
});
389389
}
390390

391391
/// An interface to an LCD controller using one sub-bank

‎src/gpio.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -450,13 +450,13 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
450450
fn _set_high(&mut self) {
451451
// NOTE(unsafe) atomic write to a stateless register
452452
let gpio = unsafe { &(*gpiox::<P>()) };
453-
gpio.bsrr().write(|w| w.bs(N).set_bit())
453+
gpio.bsrr().write(|w| w.bs(N).set_bit());
454454
}
455455
#[inline(always)]
456456
fn _set_low(&mut self) {
457457
// NOTE(unsafe) atomic write to a stateless register
458458
let gpio = unsafe { &(*gpiox::<P>()) };
459-
gpio.bsrr().write(|w| w.br(N).set_bit())
459+
gpio.bsrr().write(|w| w.br(N).set_bit());
460460
}
461461
#[inline(always)]
462462
fn _is_set_low(&self) -> bool {

‎src/gpio/outport.rs

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,17 +31,17 @@ macro_rules! out_port {
3131
#[doc=concat!("Set/reset pins according to `", $n, "` lower bits")]
3232
#[inline(never)]
3333
pub fn write(&mut self, word: u32) {
34-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::value_for_write_bsrr(word))) }
34+
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::value_for_write_bsrr(word))); }
3535
}
3636

3737
/// Set all pins to `PinState::High`
3838
pub fn all_high(&mut self) {
39-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask())) }
39+
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask())); }
4040
}
4141

4242
/// Reset all pins to `PinState::Low`
4343
pub fn all_low(&mut self) {
44-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask() << 16)) }
44+
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(Self::mask() << 16)); }
4545
}
4646
}
4747
}
@@ -88,17 +88,21 @@ impl<const P: char, const SIZE: usize> OutPortArray<P, SIZE> {
8888
unsafe {
8989
(*gpiox::<P>())
9090
.bsrr()
91-
.write(|w| w.bits(self.value_for_write_bsrr(word)))
91+
.write(|w| w.bits(self.value_for_write_bsrr(word)));
9292
}
9393
}
9494

9595
/// Set all pins to `PinState::High`
9696
pub fn all_high(&mut self) {
97-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask())) }
97+
unsafe {
98+
(*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask()));
99+
}
98100
}
99101

100102
/// Reset all pins to `PinState::Low`
101103
pub fn all_low(&mut self) {
102-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask() << 16)) }
104+
unsafe {
105+
(*gpiox::<P>()).bsrr().write(|w| w.bits(self.mask() << 16));
106+
}
103107
}
104108
}

‎src/gpio/partially_erased.rs

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,14 +68,18 @@ impl<const P: char, MODE> PartiallyErasedPin<P, Output<MODE>> {
6868
#[inline(always)]
6969
pub fn set_high(&mut self) {
7070
// NOTE(unsafe) atomic write to a stateless register
71-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << self.i)) }
71+
unsafe {
72+
(*gpiox::<P>()).bsrr().write(|w| w.bits(1 << self.i));
73+
}
7274
}
7375

7476
/// Drives the pin low
7577
#[inline(always)]
7678
pub fn set_low(&mut self) {
7779
// NOTE(unsafe) atomic write to a stateless register
78-
unsafe { (*gpiox::<P>()).bsrr().write(|w| w.bits(1 << (self.i + 16))) }
80+
unsafe {
81+
(*gpiox::<P>()).bsrr().write(|w| w.bits(1 << (self.i + 16)));
82+
}
7983
}
8084

8185
/// Is the pin in drive high or low mode?

‎src/rcc/f4/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ impl CFGR {
526526
w.prften().set_bit();
527527
w.icen().set_bit();
528528
w.dcen().set_bit()
529-
})
529+
});
530530
}
531531
}
532532

‎src/rtc.rs

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ impl Rtc {
183183
regs.prer().modify(|_, w| {
184184
w.prediv_s().set(prediv_s);
185185
w.prediv_a().set(prediv_a)
186-
})
186+
});
187187
});
188188

189189
result
@@ -261,7 +261,7 @@ impl Rtc {
261261
regs.prer().modify(|_, w| {
262262
w.prediv_s().set(prediv_s);
263263
w.prediv_a().set(prediv_a)
264-
})
264+
});
265265
});
266266
}
267267

@@ -311,7 +311,7 @@ impl Rtc {
311311
w.st().set(st);
312312
w.su().set(su);
313313
w.pm().clear_bit()
314-
})
314+
});
315315
});
316316

317317
Ok(())
@@ -324,7 +324,7 @@ impl Rtc {
324324
}
325325
let (st, su) = bcd2_encode(seconds.into())?;
326326
self.modify(true, |regs| {
327-
regs.tr().modify(|_, w| w.st().set(st).su().set(su))
327+
regs.tr().modify(|_, w| w.st().set(st).su().set(su));
328328
});
329329

330330
Ok(())
@@ -337,7 +337,7 @@ impl Rtc {
337337
}
338338
let (mnt, mnu) = bcd2_encode(minutes.into())?;
339339
self.modify(true, |regs| {
340-
regs.tr().modify(|_, w| w.mnt().set(mnt).mnu().set(mnu))
340+
regs.tr().modify(|_, w| w.mnt().set(mnt).mnu().set(mnu));
341341
});
342342

343343
Ok(())
@@ -351,7 +351,7 @@ impl Rtc {
351351
let (ht, hu) = bcd2_encode(hours.into())?;
352352

353353
self.modify(true, |regs| {
354-
regs.tr().modify(|_, w| w.ht().set(ht).hu().set(hu))
354+
regs.tr().modify(|_, w| w.ht().set(ht).hu().set(hu));
355355
});
356356

357357
Ok(())
@@ -363,7 +363,7 @@ impl Rtc {
363363
return Err(Error::InvalidInputData);
364364
}
365365
self.modify(true, |regs| {
366-
regs.dr().modify(|_, w| unsafe { w.wdu().bits(weekday) })
366+
regs.dr().modify(|_, w| unsafe { w.wdu().bits(weekday) });
367367
});
368368

369369
Ok(())
@@ -376,7 +376,7 @@ impl Rtc {
376376
}
377377
let (dt, du) = bcd2_encode(day as u32)?;
378378
self.modify(true, |regs| {
379-
regs.dr().modify(|_, w| w.dt().set(dt).du().set(du))
379+
regs.dr().modify(|_, w| w.dt().set(dt).du().set(du));
380380
});
381381

382382
Ok(())
@@ -389,7 +389,7 @@ impl Rtc {
389389
}
390390
let (mt, mu) = bcd2_encode(month as u32)?;
391391
self.modify(true, |regs| {
392-
regs.dr().modify(|_, w| w.mt().bit(mt > 0).mu().set(mu))
392+
regs.dr().modify(|_, w| w.mt().bit(mt > 0).mu().set(mu));
393393
});
394394

395395
Ok(())
@@ -405,7 +405,7 @@ impl Rtc {
405405
}
406406
let (yt, yu) = bcd2_encode(year as u32 - 1970)?;
407407
self.modify(true, |regs| {
408-
regs.dr().modify(|_, w| w.yt().set(yt).yu().set(yu))
408+
regs.dr().modify(|_, w| w.yt().set(yt).yu().set(yu));
409409
});
410410

411411
Ok(())
@@ -434,7 +434,7 @@ impl Rtc {
434434
w.yt().set(yt);
435435
w.yu().set(yu);
436436
unsafe { w.wdu().bits(wdu) }
437-
})
437+
});
438438
});
439439

440440
Ok(())
@@ -476,7 +476,7 @@ impl Rtc {
476476
w.st().set(st);
477477
w.su().set(su);
478478
w.pm().clear_bit()
479-
})
479+
});
480480
});
481481

482482
Ok(())

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