clippy

Author: burrbull

src/rcc/f4/mod.rs

@@ -1,6 +1,6 @@
 use crate::pac::rcc::cfgr::{HPRE, SW};
 use crate::pac::rcc::RegisterBlock as RccRB;
-use crate::pac::{self, rcc, RCC};
+use crate::pac::{rcc, RCC};
 
 use super::{BusClock, BusTimerClock, RccBus};
 

src/serial/uart_impls.rs

@@ -126,8 +126,7 @@ pub trait RegisterBlockImpl: UartRB {
     }
     #[inline(always)]
     fn clear_flags(&self, flags: BitFlags<CFlag>) {
-        self.sr()
-            .write(|w| unsafe { w.bits(0xffff & !flags.bits()) });
+        self.sr().write(|w| unsafe { w.bits(!flags.bits()) });
     }
     fn clear_idle_interrupt(&self) {
         let _ = self.sr().read();