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burrbullburrbull
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f2 dma
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lines changed

5 files changed

+336
-3
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‎src/dma/traits.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -302,12 +302,12 @@ pub use f7::*;
302302
mod g0;
303303
#[cfg(feature = "g0")]
304304
pub use g0::*;
305-
*/
305+
306306
#[cfg(feature = "g4")]
307307
mod g4;
308308
#[cfg(feature = "g4")]
309309
pub use g4::*;
310-
/*
310+
311311
#[cfg(feature = "h7")]
312312
mod h7;
313313
#[cfg(feature = "h7")]

‎src/dma/traits/f2.rs

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
use super::*;
2+
3+
dma_map! {
4+
(Stream0<DMA1>:0, SPI3_RX, [PeripheralToMemory]), //SPI3_RX
5+
(Stream2<DMA1>:0, SPI3_RX, [PeripheralToMemory]), //SPI3_RX
6+
(Stream3<DMA1>:0, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
7+
(Stream4<DMA1>:0, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
8+
(Stream5<DMA1>:0, SPI3_TX, [MemoryToPeripheral]), //SPI3_TX
9+
(Stream7<DMA1>:0, SPI3_TX, [MemoryToPeripheral]), //SPI3_TX
10+
(Stream0<DMA1>:1, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
11+
(Stream2<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
12+
(Stream4<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
13+
(Stream5<DMA1>:1, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
14+
(Stream6<DMA1>:1, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
15+
(Stream7<DMA1>:1, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
16+
(Stream0<DMA1>:2, TIM4_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1
17+
(Stream3<DMA1>:2, TIM4_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2
18+
(Stream6<DMA1>:2, TIM4_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP
19+
(Stream7<DMA1>:2, TIM4_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3
20+
(Stream1<DMA1>:3, TIM2_UP/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP/CH3
21+
(Stream2<DMA1>:3, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
22+
(Stream4<DMA1>:3, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
23+
(Stream5<DMA1>:3, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
24+
(Stream6<DMA1>:3, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
25+
(Stream7<DMA1>:3, TIM2_UP/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP/CH4
26+
(Stream0<DMA1>:4, UART5_RX, [PeripheralToMemory]), //UART5_RX
27+
(Stream1<DMA1>:4, USART3_RX, [PeripheralToMemory]), //USART3_RX
28+
(Stream2<DMA1>:4, UART4_RX, [PeripheralToMemory]), //UART4_RX
29+
(Stream3<DMA1>:4, USART3_TX, [MemoryToPeripheral]), //USART3_TX
30+
(Stream4<DMA1>:4, UART4_TX, [MemoryToPeripheral]), //UART4_TX
31+
(Stream5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
32+
(Stream6<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
33+
(Stream7<DMA1>:4, UART5_TX, [MemoryToPeripheral]), //UART5_TX
34+
(Stream2<DMA1>:5, TIM3_CH4/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4/UP
35+
(Stream4<DMA1>:5, TIM3_CH1/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1/TRIG
36+
(Stream5<DMA1>:5, TIM3_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2
37+
(Stream7<DMA1>:5, TIM3_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
38+
(Stream0<DMA1>:6, TIM5_CH3/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3/UP
39+
(Stream1<DMA1>:6, TIM5_CH4/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG
40+
(Stream2<DMA1>:6, TIM5_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH1
41+
(Stream3<DMA1>:6, TIM5_CH4/TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG
42+
(Stream4<DMA1>:6, TIM5_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2
43+
(Stream6<DMA1>:6, TIM5_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
44+
(Stream1<DMA1>:7, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
45+
(Stream2<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
46+
(Stream3<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
47+
(Stream4<DMA1>:7, USART3_TX:DMA_CHANNEL_7, [MemoryToPeripheral]), //USART3_TX:DMA_CHANNEL_7
48+
(Stream5<DMA1>:7, DAC1, [MemoryToPeripheral]), //DAC1
49+
(Stream6<DMA1>:7, DAC2, [MemoryToPeripheral]), //DAC2
50+
(Stream7<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
51+
(Stream0<DMA2>:0, ADC1, [PeripheralToMemory]), //ADC1
52+
(Stream2<DMA2>:0, TIM8_CH1/CH2/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1/CH2/CH3
53+
(Stream4<DMA2>:0, ADC1, [PeripheralToMemory]), //ADC1
54+
(Stream6<DMA2>:0, TIM1_CH1/CH2/CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1/CH2/CH3
55+
(Stream1<DMA2>:1, DCMI, [PeripheralToMemory]), //DCMI
56+
(Stream2<DMA2>:1, ADC2, [PeripheralToMemory]), //ADC2
57+
(Stream3<DMA2>:1, ADC2, [PeripheralToMemory]), //ADC2
58+
(Stream7<DMA2>:1, DCMI, [PeripheralToMemory]), //DCMI
59+
(Stream0<DMA2>:2, ADC3, [PeripheralToMemory]), //ADC3
60+
(Stream1<DMA2>:2, ADC3, [PeripheralToMemory]), //ADC3
61+
(Stream5<DMA2>:2, CRYP_OUT, [PeripheralToMemory]), //CRYP_OUT
62+
(Stream6<DMA2>:2, CRYP_IN, [MemoryToPeripheral]), //CRYP_IN
63+
(Stream7<DMA2>:2, HASH_IN, [MemoryToPeripheral]), //HASH_IN
64+
(Stream0<DMA2>:3, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
65+
(Stream2<DMA2>:3, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
66+
(Stream3<DMA2>:3, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
67+
(Stream5<DMA2>:3, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
68+
(Stream2<DMA2>:4, USART1_RX, [PeripheralToMemory]), //USART1_RX
69+
(Stream3<DMA2>:4, SDIO:Conflict:SDIO_RX,SDIO_TX, [MemoryToPeripheral | PeripheralToMemory]), //SDIO:Conflict:SDIO_RX,SDIO_TX
70+
(Stream3<DMA2>:4, SDIO_RX:Conflict:SDIO, [PeripheralToMemory]), //SDIO_RX:Conflict:SDIO
71+
(Stream3<DMA2>:4, SDIO_TX:Conflict:SDIO, [MemoryToPeripheral]), //SDIO_TX:Conflict:SDIO
72+
(Stream5<DMA2>:4, USART1_RX, [PeripheralToMemory]), //USART1_RX
73+
(Stream6<DMA2>:4, SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO
74+
(Stream6<DMA2>:4, SDIO_RX, [PeripheralToMemory]), //SDIO_RX
75+
(Stream6<DMA2>:4, SDIO_TX, [MemoryToPeripheral]), //SDIO_TX
76+
(Stream7<DMA2>:4, USART1_TX, [MemoryToPeripheral]), //USART1_TX
77+
(Stream1<DMA2>:5, USART6_RX, [PeripheralToMemory]), //USART6_RX
78+
(Stream2<DMA2>:5, USART6_RX, [PeripheralToMemory]), //USART6_RX
79+
(Stream6<DMA2>:5, USART6_TX, [MemoryToPeripheral]), //USART6_TX
80+
(Stream7<DMA2>:5, USART6_TX, [MemoryToPeripheral]), //USART6_TX
81+
(Stream0<DMA2>:6, TIM1_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
82+
(Stream1<DMA2>:6, TIM1_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
83+
(Stream2<DMA2>:6, TIM1_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
84+
(Stream3<DMA2>:6, TIM1_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
85+
(Stream4<DMA2>:6, TIM1_CH4/TRIG/COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4/TRIG/COM
86+
(Stream5<DMA2>:6, TIM1_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP
87+
(Stream6<DMA2>:6, TIM1_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
88+
(Stream1<DMA2>:7, TIM8_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_UP
89+
(Stream2<DMA2>:7, TIM8_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1
90+
(Stream3<DMA2>:7, TIM8_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2
91+
(Stream4<DMA2>:7, TIM8_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3
92+
(Stream7<DMA2>:7, TIM8_CH4/TRIG/COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH4/TRIG/COM
93+
}

‎src/dma/traits/g4.rs

Lines changed: 0 additions & 1 deletion
This file was deleted.

‎src/dma/traits/l0.rs

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,133 @@
1+
use super::*;
2+
3+
#[cfg(feature = "STM32L021_dma_v1_1")]
4+
dma_map! {
5+
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
6+
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
7+
(Channel4<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
8+
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
9+
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
10+
(Channel4<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
11+
(Channel5<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
12+
(Channel2<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
13+
(Channel3<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
14+
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
15+
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
16+
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
17+
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
18+
(Channel4<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
19+
(Channel5<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
20+
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
21+
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
22+
(Channel4<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
23+
(Channel5<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
24+
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
25+
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
26+
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
27+
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
28+
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
29+
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
30+
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
31+
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
32+
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
33+
}
34+
#[cfg(feature = "STM32L063_dma_v1_1")]
35+
dma_map! {
36+
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
37+
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
38+
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
39+
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
40+
(Channel4<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
41+
(Channel5<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
42+
(Channel6<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
43+
(Channel7<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
44+
(Channel2<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
45+
(Channel3<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
46+
(Channel4<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
47+
(Channel5<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
48+
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
49+
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
50+
(Channel6<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
51+
(Channel7<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
52+
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
53+
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
54+
(Channel6<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
55+
(Channel7<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
56+
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
57+
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
58+
(Channel6<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
59+
(Channel7<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
60+
(Channel4<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
61+
(Channel5<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
62+
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
63+
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
64+
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
65+
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
66+
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
67+
(Channel7<DMA1>:8, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
68+
(Channel2<DMA1>:9, DAC_CH1, [MemoryToPeripheral]), //DAC_CH1
69+
(Channel2<DMA1>:9, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
70+
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
71+
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
72+
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
73+
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
74+
}
75+
#[cfg(feature = "STM32L083_dma_v1_1")]
76+
dma_map! {
77+
(Channel1<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
78+
(Channel2<DMA1>:0, ADC, [PeripheralToMemory]), //ADC
79+
(Channel2<DMA1>:1, SPI1_RX, [PeripheralToMemory]), //SPI1_RX
80+
(Channel3<DMA1>:1, SPI1_TX, [MemoryToPeripheral]), //SPI1_TX
81+
(Channel4<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
82+
(Channel5<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
83+
(Channel6<DMA1>:2, SPI2_RX, [PeripheralToMemory]), //SPI2_RX
84+
(Channel7<DMA1>:2, SPI2_TX, [MemoryToPeripheral]), //SPI2_TX
85+
(Channel2<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
86+
(Channel3<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
87+
(Channel4<DMA1>:3, USART1_TX, [MemoryToPeripheral]), //USART1_TX
88+
(Channel5<DMA1>:3, USART1_RX, [PeripheralToMemory]), //USART1_RX
89+
(Channel4<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
90+
(Channel5<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
91+
(Channel6<DMA1>:4, USART2_RX, [PeripheralToMemory]), //USART2_RX
92+
(Channel7<DMA1>:4, USART2_TX, [MemoryToPeripheral]), //USART2_TX
93+
(Channel2<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
94+
(Channel3<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
95+
(Channel6<DMA1>:5, LPUART1_RX, [PeripheralToMemory]), //LPUART1_RX
96+
(Channel7<DMA1>:5, LPUART1_TX, [MemoryToPeripheral]), //LPUART1_TX
97+
(Channel2<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
98+
(Channel3<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
99+
(Channel6<DMA1>:6, I2C1_TX, [MemoryToPeripheral]), //I2C1_TX
100+
(Channel7<DMA1>:6, I2C1_RX, [PeripheralToMemory]), //I2C1_RX
101+
(Channel4<DMA1>:7, I2C2_TX, [MemoryToPeripheral]), //I2C2_TX
102+
(Channel5<DMA1>:7, I2C2_RX, [PeripheralToMemory]), //I2C2_RX
103+
(Channel1<DMA1>:8, TIM2_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
104+
(Channel2<DMA1>:8, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
105+
(Channel3<DMA1>:8, TIM2_CH2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
106+
(Channel4<DMA1>:8, TIM2_CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
107+
(Channel5<DMA1>:8, TIM2_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
108+
(Channel7<DMA1>:8, TIM2_CH2/CH4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2/CH4
109+
(Channel2<DMA1>:9, DAC_CH1, [MemoryToPeripheral]), //DAC_CH1
110+
(Channel2<DMA1>:9, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
111+
(Channel2<DMA1>:10, TIM3_CH3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
112+
(Channel3<DMA1>:10, TIM3_CH4/UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4/UP
113+
(Channel5<DMA1>:10, TIM3_CH1, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1
114+
(Channel6<DMA1>:10, TIM3_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG
115+
(Channel1<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
116+
(Channel2<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
117+
(Channel3<DMA1>:11, AES_OUT, [PeripheralToMemory]), //AES_OUT
118+
(Channel5<DMA1>:11, AES_IN, [MemoryToPeripheral]), //AES_IN
119+
(Channel2<DMA1>:12, USART4_RX, [PeripheralToMemory]), //USART4_RX
120+
(Channel3<DMA1>:12, USART4_TX, [MemoryToPeripheral]), //USART4_TX
121+
(Channel6<DMA1>:12, USART4_RX, [PeripheralToMemory]), //USART4_RX
122+
(Channel7<DMA1>:12, USART4_TX, [MemoryToPeripheral]), //USART4_TX
123+
(Channel2<DMA1>:13, USART5_RX, [PeripheralToMemory]), //USART5_RX
124+
(Channel3<DMA1>:13, USART5_TX, [MemoryToPeripheral]), //USART5_TX
125+
(Channel6<DMA1>:13, USART5_RX, [PeripheralToMemory]), //USART5_RX
126+
(Channel7<DMA1>:13, USART5_TX, [MemoryToPeripheral]), //USART5_TX
127+
(Channel2<DMA1>:14, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
128+
(Channel3<DMA1>:14, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
129+
(Channel4<DMA1>:14, I2C3_TX, [MemoryToPeripheral]), //I2C3_TX
130+
(Channel5<DMA1>:14, I2C3_RX, [PeripheralToMemory]), //I2C3_RX
131+
(Channel4<DMA1>:15, DAC_CH2, [MemoryToPeripheral]), //DAC_CH2
132+
(Channel4<DMA1>:15, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
133+
}

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