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Merge pull request #821 from stm32-rs/fix-monotonics
fix monotonics
2 parents ff78db4 + a7b2970 commit c3eb268

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2 files changed

+17
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CHANGELOG.md

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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- Fix pac `defmt` feature
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- Fix timer interrupt status clear
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## [v0.22.0] - 2024-10-04
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src/timer/monotonics.rs

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Original file line numberDiff line numberDiff line change
@@ -178,7 +178,10 @@ macro_rules! make_timer {
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// The above line raises an update event which will indicate that the timer is already finished.
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// Since this is not the case, it should be cleared.
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self.tim.sr().modify(|_, w| w.uif().clear_bit());
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self.tim.sr().write(|w| {
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unsafe { w.bits(!0) };
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w.uif().clear_bit()
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});
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$tq.initialize(MonoTimerBackend::<pac::$timer> { _tim: PhantomData });
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$overflow.store(0, Ordering::SeqCst);
@@ -231,7 +234,10 @@ macro_rules! make_timer {
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}
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fn clear_compare_flag() {
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Self::tim().sr().modify(|_, w| w.cc2if().clear_bit());
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Self::tim().sr().write(|w| {
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unsafe { w.bits(!0) };
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w.cc2if().clear_bit()
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});
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}
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fn pend_interrupt() {
@@ -249,13 +255,19 @@ macro_rules! make_timer {
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fn on_interrupt() {
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// Full period
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if Self::tim().sr().read().uif().bit_is_set() {
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Self::tim().sr().modify(|_, w| w.uif().clear_bit());
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Self::tim().sr().write(|w| {
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unsafe { w.bits(!0) };
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w.uif().clear_bit()
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});
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let prev = $overflow.fetch_add(1, Ordering::Relaxed);
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assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!");
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}
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// Half period
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if Self::tim().sr().read().cc1if().bit_is_set() {
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Self::tim().sr().modify(|_, w| w.cc1if().clear_bit());
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Self::tim().sr().write(|w| {
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unsafe { w.bits(!0) };
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w.cc1if().clear_bit()
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});
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let prev = $overflow.fetch_add(1, Ordering::Relaxed);
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assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!");
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}

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