clippy + msrv 1.62

Author: burrbull

CHANGELOG.md

@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+ - Bump MSRV to 1.62
  - Use `stm32f4-staging` until `stm32f4` is released [#706]
  - RTIC2 monotonics fix: CC1 instead of CC3
  - Allow different lengths of buffers in hal_1 SpiBus impl [#566]

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 edition = "2021"
-rust-version = "1.60"
+rust-version = "1.62"
 
 authors = ["Daniel Egger <daniel@eggers-club.de>"]
 categories = ["embedded", "hardware-support", "no-std"]

README.md

@@ -4,7 +4,7 @@ stm32f4xx-hal
 [![Crates.io](https://img.shields.io/crates/d/stm32f4xx-hal.svg)](https://crates.io/crates/stm32f4xx-hal)
 [![Crates.io](https://img.shields.io/crates/v/stm32f4xx-hal.svg)](https://crates.io/crates/stm32f4xx-hal)
 [![Released API docs](https://docs.rs/stm32f4xx-hal/badge.svg)](https://docs.rs/stm32f4xx-hal)
-![Minimum Supported Rust Version](https://img.shields.io/badge/rustc-1.60+-blue.svg)
+![Minimum Supported Rust Version](https://img.shields.io/badge/rustc-1.62+-blue.svg)
 [![dependency status](https://deps.rs/repo/github/stm32-rs/stm32f4xx-hal/status.svg)](https://deps.rs/repo/github/stm32-rs/stm32f4xx-hal)
 [![Continuous integration](https://github.com/stm32-rs/stm32f4xx-hal/workflows/Continuous%20integration/badge.svg)](https://github.com/stm32-rs/stm32f4xx-hal)
 

src/adc.rs

@@ -448,8 +448,8 @@ macro_rules! adc {
                 /// # Arguments
                 /// * `channel` - channel to configure
                 /// * `sequence` - where in the sequence to sample the channel. Also called rank in some STM docs/code
-                /// * `sample_time` - how long to sample for. See datasheet and ref manual to work out how long you need\
-                /// to sample for at a given ADC clock frequency
+                /// * `sample_time` - how long to sample for. See datasheet and ref manual to work out how long you need
+                ///   to sample for at a given ADC clock frequency
                 pub fn configure_channel<CHANNEL>(&mut self, _channel: &CHANNEL, sequence: config::Sequence, sample_time: config::SampleTime)
                 where
                     CHANNEL: embedded_hal_02::adc::Channel<pac::$adc_type, ID=u8>

src/dma/mod.rs

@@ -1318,7 +1318,7 @@ where
     /// # Panics
     ///
     /// * When the FIFO is disabled or double buffering is enabled in `DmaConfig` while initializing
-    /// a memory to memory transfer.
+    ///   a memory to memory transfer.
     pub fn init_memory_to_memory(
         mut stream: STREAM,
         peripheral: PERIPHERAL,

src/dwt.rs

@@ -69,21 +69,21 @@ impl Delay {
     /// Delay ticks
     /// NOTE DCB and DWT need to be set up for this to work, so it is private
     fn delay_ticks(mut start: u32, ticks: u64) {
-        if ticks < (core::u32::MAX / 2) as u64 {
+        if ticks < (u32::MAX / 2) as u64 {
             // Simple delay
             let ticks = ticks as u32;
             while (DWT::cycle_count().wrapping_sub(start)) < ticks {}
-        } else if ticks <= core::u32::MAX as u64 {
+        } else if ticks <= u32::MAX as u64 {
             // Try to avoid race conditions by limiting delay to u32::MAX / 2
             let mut ticks = ticks as u32;
-            ticks -= core::u32::MAX / 2;
-            while (DWT::cycle_count().wrapping_sub(start)) < core::u32::MAX / 2 {}
-            start -= core::u32::MAX / 2;
+            ticks -= u32::MAX / 2;
+            while (DWT::cycle_count().wrapping_sub(start)) < u32::MAX / 2 {}
+            start -= u32::MAX / 2;
             while (DWT::cycle_count().wrapping_sub(start)) < ticks {}
         } else {
             // Delay for ticks, then delay for rest * u32::MAX
             let mut rest = (ticks >> 32) as u32;
-            let ticks = (ticks & core::u32::MAX as u64) as u32;
+            let ticks = (ticks & u32::MAX as u64) as u32;
             loop {
                 while (DWT::cycle_count().wrapping_sub(start)) < ticks {}
                 if rest == 0 {

src/gpio.rs

@@ -27,14 +27,14 @@
 //! - **Dynamic**: Pin mode is selected at runtime. See changing configurations for more details
 //! - Input
 //!     - **PullUp**: Input connected to high with a weak pull up resistor. Will be high when nothing
-//!     is connected
+//!       is connected
 //!     - **PullDown**: Input connected to high with a weak pull up resistor. Will be low when nothing
-//!     is connected
+//!       is connected
 //!     - **Floating**: Input not pulled to high or low. Will be undefined when nothing is connected
 //! - Output
 //!     - **PushPull**: Output which either drives the pin high or low
 //!     - **OpenDrain**: Output which leaves the gate floating, or pulls it do ground in drain
-//!     mode. Can be used as an input in the `open` configuration
+//!       mode. Can be used as an input in the `open` configuration
 //!
 //! ## Changing modes
 //! The simplest way to change the pin mode is to use the `into_<mode>` functions. These return a

src/timer/pwm_input.rs

@@ -9,6 +9,7 @@ use fugit::HertzU32 as Hertz;
 /// This peripheral will emit an interrupt on CC2 events, which occurs at two times in this mode:
 /// 1. When a new cycle is started: the duty cycle will be `1.00`
 /// 2. When the period is captured. the duty cycle will be an observable value.
+///
 /// An example interrupt handler is provided:
 /// ```
 /// use stm32f4xx_hal::{pac::TIM8, pwm_input::PwmInput};
@@ -74,6 +75,7 @@ macro_rules! hal {
             /// This device will emit an interrupt on CC1, which occurs at two times in this mode:
             /// 1. When a new cycle is started: the duty cycle will be `1.00`
             /// 2. When the period is captured. the duty cycle will be an observable value.
+            ///
             /// See the pwm input example for an suitable interrupt handler.
             pub fn pwm_input(
                 mut self,