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‎src/dma/mod.rs

Lines changed: 68 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ use core::{
1818
use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
1919

2020
use crate::pac::RCC;
21-
use crate::rcc;
21+
use crate::{pac, rcc};
2222

2323
pub mod traits;
2424
use traits::{
@@ -211,6 +211,29 @@ impl<DMA, const S: u8> StreamX<DMA, S> {
211211
}
212212
}
213213

214+
impl<DMA: Instance, const S: u8> StreamX<DMA, S> {
215+
#[cfg(not(any(
216+
feature = "stm32f411",
217+
feature = "stm32f413",
218+
feature = "stm32f423",
219+
feature = "stm32f410"
220+
)))]
221+
#[inline(always)]
222+
unsafe fn st() -> &'static pac::dma2::ST {
223+
&(*DMA::ptr()).st[S as usize]
224+
}
225+
#[cfg(any(
226+
feature = "stm32f411",
227+
feature = "stm32f413",
228+
feature = "stm32f423",
229+
feature = "stm32f410"
230+
))]
231+
#[inline(always)]
232+
unsafe fn st() -> &'static pac::dma1::ST {
233+
&(*DMA::ptr()).st[S as usize]
234+
}
235+
}
236+
214237
/// Stream 0 on the DMA controller.
215238
pub type Stream0<DMA> = StreamX<DMA, 0>;
216239
/// Stream 1 on the DMA controller.
@@ -238,25 +261,25 @@ impl<DMA> Sealed for StreamX<DMA, 6> {}
238261
impl<DMA> Sealed for StreamX<DMA, 7> {}
239262

240263
/// Alias for a tuple with all DMA streams.
241-
pub struct StreamsTuple<T>(
242-
pub StreamX<T, 0>,
243-
pub StreamX<T, 1>,
244-
pub StreamX<T, 2>,
245-
pub StreamX<T, 3>,
246-
pub StreamX<T, 4>,
247-
pub StreamX<T, 5>,
248-
pub StreamX<T, 6>,
249-
pub StreamX<T, 7>,
264+
pub struct StreamsTuple<DMA>(
265+
pub StreamX<DMA, 0>,
266+
pub StreamX<DMA, 1>,
267+
pub StreamX<DMA, 2>,
268+
pub StreamX<DMA, 3>,
269+
pub StreamX<DMA, 4>,
270+
pub StreamX<DMA, 5>,
271+
pub StreamX<DMA, 6>,
272+
pub StreamX<DMA, 7>,
250273
);
251274

252-
impl<T: rcc::Enable + rcc::Reset> StreamsTuple<T> {
275+
impl<DMA: rcc::Enable + rcc::Reset> StreamsTuple<DMA> {
253276
/// Splits the DMA peripheral into streams.
254-
pub fn new(_regs: T) -> Self {
277+
pub fn new(_regs: DMA) -> Self {
255278
unsafe {
256279
//NOTE(unsafe) this reference will only be used for atomic writes with no side effects
257280
let rcc = &(*RCC::ptr());
258-
T::enable(rcc);
259-
T::reset(rcc);
281+
DMA::enable(rcc);
282+
DMA::reset(rcc);
260283
}
261284
Self(
262285
StreamX::new(),
@@ -279,84 +302,63 @@ where
279302

280303
#[inline(always)]
281304
fn set_peripheral_address(&mut self, value: u32) {
282-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
283-
let dma = unsafe { &*I::ptr() };
284-
dma.st[Self::NUMBER]
305+
unsafe { Self::st() }
285306
.par
286307
.write(|w| unsafe { w.pa().bits(value) });
287308
}
288309

289310
#[inline(always)]
290311
fn set_memory_address(&mut self, value: u32) {
291-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
292-
let dma = unsafe { &*I::ptr() };
293-
dma.st[Self::NUMBER]
312+
unsafe { Self::st() }
294313
.m0ar
295314
.write(|w| unsafe { w.m0a().bits(value) });
296315
}
297316

298317
#[inline(always)]
299318
fn get_memory_address(&self) -> u32 {
300-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
301-
let dma = unsafe { &*I::ptr() };
302-
dma.st[Self::NUMBER].m0ar.read().m0a().bits()
319+
unsafe { Self::st() }.m0ar.read().m0a().bits()
303320
}
304321

305322
#[inline(always)]
306323
fn set_memory_double_buffer_address(&mut self, value: u32) {
307-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
308-
let dma = unsafe { &*I::ptr() };
309-
dma.st[Self::NUMBER]
324+
unsafe { Self::st() }
310325
.m1ar
311326
.write(|w| unsafe { w.m1a().bits(value) });
312327
}
313328

314329
#[inline(always)]
315330
fn get_memory_double_buffer_address(&self) -> u32 {
316-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
317-
let dma = unsafe { &*I::ptr() };
318-
dma.st[Self::NUMBER].m1ar.read().m1a().bits()
331+
unsafe { Self::st() }.m1ar.read().m1a().bits()
319332
}
320333

321334
#[inline(always)]
322335
fn set_number_of_transfers(&mut self, value: u16) {
323-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
324-
let dma = unsafe { &*I::ptr() };
325-
dma.st[Self::NUMBER].ndtr.write(|w| w.ndt().bits(value));
336+
unsafe { Self::st() }.ndtr.write(|w| w.ndt().bits(value));
326337
}
327338

328339
#[inline(always)]
329340
fn get_number_of_transfers() -> u16 {
330-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
331-
let dma = unsafe { &*I::ptr() };
332-
dma.st[Self::NUMBER].ndtr.read().ndt().bits()
341+
unsafe { Self::st() }.ndtr.read().ndt().bits()
333342
}
334343

335344
#[inline(always)]
336345
unsafe fn enable(&mut self) {
337-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
338-
let dma = &*I::ptr();
339-
dma.st[Self::NUMBER].cr.modify(|_, w| w.en().set_bit());
346+
Self::st().cr.modify(|_, w| w.en().set_bit());
340347
}
341348

342349
#[inline(always)]
343350
fn is_enabled() -> bool {
344-
//NOTE(unsafe) Atomic read with no side effects
345-
let dma = unsafe { &*I::ptr() };
346-
dma.st[Self::NUMBER].cr.read().en().bit_is_set()
351+
unsafe { Self::st() }.cr.read().en().bit_is_set()
347352
}
348353

349354
fn disable(&mut self) {
350355
if Self::is_enabled() {
351-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
352-
let dma = unsafe { &*I::ptr() };
353-
354356
// Aborting an on-going transfer might cause interrupts to fire, disable
355357
// them
356358
let (tc, ht, te, dm) = Self::get_interrupts_enable();
357359
self.set_interrupts_enable(false, false, false, false);
358360

359-
dma.st[Self::NUMBER].cr.modify(|_, w| w.en().clear_bit());
361+
unsafe { Self::st() }.cr.modify(|_, w| w.en().clear_bit());
360362
while Self::is_enabled() {}
361363

362364
self.clear_interrupts();
@@ -366,59 +368,45 @@ where
366368

367369
#[inline(always)]
368370
fn set_channel<C: Channel>(&mut self, channel: C) {
369-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
370-
let dma = unsafe { &*I::ptr() };
371-
dma.st[Self::NUMBER]
371+
unsafe { Self::st() }
372372
.cr
373373
.modify(|_, w| w.chsel().bits(channel.bits()));
374374
}
375375

376376
#[inline(always)]
377377
fn set_priority(&mut self, priority: config::Priority) {
378-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
379-
let dma = unsafe { &*I::ptr() };
380-
dma.st[Self::NUMBER]
378+
unsafe { Self::st() }
381379
.cr
382380
.modify(|_, w| w.pl().bits(priority.bits()));
383381
}
384382

385383
#[inline(always)]
386384
unsafe fn set_memory_size(&mut self, size: u8) {
387-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
388-
let dma = &*I::ptr();
389-
dma.st[Self::NUMBER].cr.modify(|_, w| w.msize().bits(size));
385+
Self::st().cr.modify(|_, w| w.msize().bits(size));
390386
}
391387

392388
#[inline(always)]
393389
unsafe fn set_peripheral_size(&mut self, size: u8) {
394-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
395-
let dma = &*I::ptr();
396-
dma.st[Self::NUMBER].cr.modify(|_, w| w.psize().bits(size));
390+
Self::st().cr.modify(|_, w| w.psize().bits(size));
397391
}
398392

399393
#[inline(always)]
400394
fn set_memory_increment(&mut self, increment: bool) {
401-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
402-
let dma = unsafe { &*I::ptr() };
403-
dma.st[Self::NUMBER]
395+
unsafe { Self::st() }
404396
.cr
405397
.modify(|_, w| w.minc().bit(increment));
406398
}
407399

408400
#[inline(always)]
409401
fn set_peripheral_increment(&mut self, increment: bool) {
410-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
411-
let dma = unsafe { &*I::ptr() };
412-
dma.st[Self::NUMBER]
402+
unsafe { Self::st() }
413403
.cr
414404
.modify(|_, w| w.pinc().bit(increment));
415405
}
416406

417407
#[inline(always)]
418408
fn set_direction<D: Direction>(&mut self, direction: D) {
419-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
420-
let dma = unsafe { &*I::ptr() };
421-
dma.st[Self::NUMBER]
409+
unsafe { Self::st() }
422410
.cr
423411
.modify(|_, w| unsafe { w.dir().bits(direction.bits()) });
424412
}
@@ -431,9 +419,7 @@ where
431419
transfer_error: bool,
432420
direct_mode_error: bool,
433421
) {
434-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
435-
let dma = unsafe { &*I::ptr() };
436-
dma.st[Self::NUMBER].cr.modify(|_, w| {
422+
unsafe { Self::st() }.cr.modify(|_, w| {
437423
w.tcie()
438424
.bit(transfer_complete)
439425
.htie()
@@ -447,9 +433,7 @@ where
447433

448434
#[inline(always)]
449435
fn get_interrupts_enable() -> (bool, bool, bool, bool) {
450-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
451-
let dma = unsafe { &*I::ptr() };
452-
let cr = dma.st[Self::NUMBER].cr.read();
436+
let cr = unsafe { Self::st() }.cr.read();
453437
(
454438
cr.tcie().bit_is_set(),
455439
cr.htie().bit_is_set(),
@@ -460,106 +444,82 @@ where
460444

461445
#[inline(always)]
462446
fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool) {
463-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
464-
let dma = unsafe { &*I::ptr() };
465-
dma.st[Self::NUMBER]
447+
unsafe { Self::st() }
466448
.cr
467449
.modify(|_, w| w.tcie().bit(transfer_complete_interrupt));
468450
}
469451

470452
#[inline(always)]
471453
fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) {
472-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
473-
let dma = unsafe { &*I::ptr() };
474-
dma.st[Self::NUMBER]
454+
unsafe { Self::st() }
475455
.cr
476456
.modify(|_, w| w.htie().bit(half_transfer_interrupt));
477457
}
478458

479459
#[inline(always)]
480460
fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool) {
481-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
482-
let dma = unsafe { &*I::ptr() };
483-
dma.st[Self::NUMBER]
461+
unsafe { Self::st() }
484462
.cr
485463
.modify(|_, w| w.teie().bit(transfer_error_interrupt));
486464
}
487465

488466
#[inline(always)]
489467
fn set_direct_mode_error_interrupt_enable(&mut self, direct_mode_error_interrupt: bool) {
490-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
491-
let dma = unsafe { &*I::ptr() };
492-
dma.st[Self::NUMBER]
468+
unsafe { Self::st() }
493469
.cr
494470
.modify(|_, w| w.dmeie().bit(direct_mode_error_interrupt));
495471
}
496472

497473
#[inline(always)]
498474
fn set_fifo_error_interrupt_enable(&mut self, fifo_error_interrupt: bool) {
499-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
500-
let dma = unsafe { &*I::ptr() };
501-
dma.st[Self::NUMBER]
475+
unsafe { Self::st() }
502476
.fcr
503477
.modify(|_, w| w.feie().bit(fifo_error_interrupt));
504478
}
505479

506480
#[inline(always)]
507481
fn set_double_buffer(&mut self, double_buffer: bool) {
508-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
509-
let dma = unsafe { &*I::ptr() };
510-
dma.st[Self::NUMBER]
482+
unsafe { Self::st() }
511483
.cr
512484
.modify(|_, w| w.dbm().bit(double_buffer));
513485
}
514486

515487
#[inline(always)]
516488
fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) {
517-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
518-
let dma = unsafe { &*I::ptr() };
519-
dma.st[Self::NUMBER]
489+
unsafe { Self::st() }
520490
.fcr
521491
.modify(|_, w| w.fth().bits(fifo_threshold.bits()));
522492
}
523493

524494
#[inline(always)]
525495
fn set_fifo_enable(&mut self, fifo_enable: bool) {
526-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
527-
let dma = unsafe { &*I::ptr() };
528496
//Register is actually direct mode disable rather than fifo enable
529-
dma.st[Self::NUMBER]
497+
unsafe { Self::st() }
530498
.fcr
531499
.modify(|_, w| w.dmdis().bit(fifo_enable));
532500
}
533501

534502
#[inline(always)]
535503
fn set_memory_burst(&mut self, memory_burst: config::BurstMode) {
536-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
537-
let dma = unsafe { &*I::ptr() };
538-
dma.st[Self::NUMBER]
504+
unsafe { Self::st() }
539505
.cr
540506
.modify(|_, w| w.mburst().bits(memory_burst.bits()));
541507
}
542508

543509
#[inline(always)]
544510
fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) {
545-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
546-
let dma = unsafe { &*I::ptr() };
547-
dma.st[Self::NUMBER]
511+
unsafe { Self::st() }
548512
.cr
549513
.modify(|_, w| w.pburst().bits(peripheral_burst.bits()));
550514
}
551515

552516
#[inline(always)]
553517
fn fifo_level() -> FifoLevel {
554-
//NOTE(unsafe) Atomic read with no side effects
555-
let dma = unsafe { &*I::ptr() };
556-
dma.st[Self::NUMBER].fcr.read().fs().bits().into()
518+
unsafe { Self::st() }.fcr.read().fs().bits().into()
557519
}
558520

559521
fn current_buffer() -> CurrentBuffer {
560-
//NOTE(unsafe) Atomic read with no side effects
561-
let dma = unsafe { &*I::ptr() };
562-
if dma.st[Self::NUMBER].cr.read().ct().bit_is_set() {
522+
if unsafe { Self::st() }.cr.read().ct().bit_is_set() {
563523
CurrentBuffer::DoubleBuffer
564524
} else {
565525
CurrentBuffer::FirstBuffer

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