Fix mstr bit for SPI Master/Slave

Author: qwerty19106

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+ - Fix mstr bit for SPI Master/Slave [#625]
  - Add `ReadPin`, `PinSpeed` & `PinPull` traits [#623]
  - Add autoimplementations of `DMASet` [#614]
  - Simplify `gpio::Outport` [#611]

src/spi.rs

@@ -319,8 +319,6 @@ impl<SPI: Instance, const BIDI: bool, W: FrameSize> Spi<SPI, BIDI, W> {
             // bidimode: 2-line or 1-line unidirectional
             w.bidimode().bit(BIDI);
             w.bidioe().bit(BIDI);
-            // master/slave mode
-            w.mstr().clear_bit();
             // data frame size
             w.dff().bit(W::DFF);
             // spe: enable the SPI bus
@@ -337,8 +335,6 @@ impl<SPI: Instance, const BIDI: bool, W: FrameSize> SpiSlave<SPI, BIDI, W> {
             // bidimode: 2-line or 1-line unidirectional
             w.bidimode().bit(BIDI);
             w.bidioe().bit(BIDI);
-            // master/slave mode
-            w.mstr().set_bit();
             // data frame size
             w.dff().bit(W::DFF);
             // spe: enable the SPI bus