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| 1 | +//! Delay implementation based on general-purpose 32 bit timers. |
| 2 | +//! |
| 3 | +//! TIM2 and TIM5 are a general purpose 32-bit auto-reload up/downcounter with |
| 4 | +//! a 16-bit prescaler. |
| 5 | +
|
| 6 | +use core::cmp::max; |
| 7 | + |
| 8 | +use cast::{u16, u32}; |
| 9 | +use embedded_hal::blocking::delay::{DelayMs, DelayUs}; |
| 10 | + |
| 11 | +use crate::{ |
| 12 | + bb, |
| 13 | + pac::{self, RCC}, |
| 14 | + rcc::Clocks, |
| 15 | +}; |
| 16 | + |
| 17 | +macro_rules! hal { |
| 18 | + ($($TIM:ident: ($struct:ident, $waitfn:ident, $en_bit:expr, $apbenr:ident, $apbrstr:ident, $pclk:ident, $ppre:ident),)+) => { |
| 19 | + $( |
| 20 | + /// General purpose timer as delay provider |
| 21 | + pub struct $struct { |
| 22 | + clocks: Clocks, |
| 23 | + tim: pac::$TIM, |
| 24 | + } |
| 25 | + |
| 26 | + fn $waitfn(tim: &mut pac::$TIM, prescaler: u16, auto_reload_register: u32) { |
| 27 | + // Write Prescaler (PSC) |
| 28 | + tim.psc.write(|w| w.psc().bits(prescaler)); |
| 29 | + |
| 30 | + // Write Auto-Reload Register (ARR) |
| 31 | + // Note: Make it impossible to set the ARR value to 0, since this |
| 32 | + // would cause an infinite loop. |
| 33 | + tim.arr.write(|w| unsafe { w.bits(max(1, auto_reload_register)) }); |
| 34 | + |
| 35 | + // Trigger update event (UEV) in the event generation register (EGR) |
| 36 | + // in order to immediately apply the config |
| 37 | + tim.cr1.modify(|_, w| w.urs().set_bit()); |
| 38 | + tim.egr.write(|w| w.ug().set_bit()); |
| 39 | + tim.cr1.modify(|_, w| w.urs().clear_bit()); |
| 40 | + |
| 41 | + // Configure the counter in one-pulse mode (counter stops counting at |
| 42 | + // the next updateevent, clearing the CEN bit) and enable the counter. |
| 43 | + tim.cr1.write(|w| w.opm().set_bit().cen().set_bit()); |
| 44 | + |
| 45 | + // Wait for CEN bit to clear |
| 46 | + while tim.cr1.read().cen().is_enabled() { /* wait */ } |
| 47 | + } |
| 48 | + |
| 49 | + impl $struct { |
| 50 | + /// Configures the timer as a delay provider |
| 51 | + pub fn new(tim: pac::$TIM, clocks: Clocks) -> Self { |
| 52 | + unsafe { |
| 53 | + //NOTE(unsafe) this reference will only be used for atomic writes with no side effects |
| 54 | + let rcc = &(*RCC::ptr()); |
| 55 | + |
| 56 | + // Enable timer peripheral in RCC |
| 57 | + bb::set(&rcc.$apbenr, $en_bit); |
| 58 | + |
| 59 | + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) |
| 60 | + cortex_m::asm::dsb(); |
| 61 | + |
| 62 | + // Reset timer |
| 63 | + bb::set(&rcc.$apbrstr, $en_bit); |
| 64 | + bb::clear(&rcc.$apbrstr, $en_bit); |
| 65 | + } |
| 66 | + |
| 67 | + // Enable one-pulse mode (counter stops counting at the next update |
| 68 | + // event, clearing the CEN bit) |
| 69 | + tim.cr1.modify(|_, w| w.opm().enabled()); |
| 70 | + |
| 71 | + Self { tim, clocks } |
| 72 | + } |
| 73 | + |
| 74 | + /// Releases the timer resource |
| 75 | + pub fn free(self) -> pac::$TIM { |
| 76 | + self.tim |
| 77 | + } |
| 78 | + } |
| 79 | + |
| 80 | + impl DelayUs<u32> for $struct { |
| 81 | + /// Sleep for up to 2^32-1 microseconds (~71 minutes). |
| 82 | + fn delay_us(&mut self, us: u32) { |
| 83 | + // Set up prescaler so that a tick takes exactly 1 µs. |
| 84 | + // |
| 85 | + // For example, if the clock is set to 48 MHz, with a prescaler of 48 |
| 86 | + // we'll get ticks that are 1 µs long. This means that we can write the |
| 87 | + // delay value directly to the auto-reload register (ARR). |
| 88 | + let psc = u16(self.clocks.pclk1().0 / 1_000_000) |
| 89 | + .expect("Prescaler does not fit in u16"); |
| 90 | + let arr = us; |
| 91 | + $waitfn(&mut self.tim, psc, arr); |
| 92 | + } |
| 93 | + } |
| 94 | + |
| 95 | + impl DelayUs<u16> for $struct { |
| 96 | + /// Sleep for up to 2^16-1 microseconds (~65 milliseconds). |
| 97 | + fn delay_us(&mut self, us: u16) { |
| 98 | + // See DelayUs<u32> for explanations. |
| 99 | + let psc = u16(self.clocks.pclk1().0 / 1_000_000) |
| 100 | + .expect("Prescaler does not fit in u16"); |
| 101 | + let arr = u32(us); |
| 102 | + $waitfn(&mut self.tim, psc, arr); |
| 103 | + } |
| 104 | + } |
| 105 | + |
| 106 | + impl DelayMs<u32> for $struct { |
| 107 | + /// Sleep for up to (2^32)/2-1 milliseconds (~24 days). |
| 108 | + /// If the `ms` value is larger than 2147483647, the code will panic. |
| 109 | + fn delay_ms(&mut self, ms: u32) { |
| 110 | + // See next section for explanation why the usable range is reduced. |
| 111 | + assert!(ms <= 2_147_483_647); // (2^32)/2-1 |
| 112 | + |
| 113 | + // Set up prescaler so that a tick takes exactly 0.5 ms. |
| 114 | + // |
| 115 | + // For example, if the clock is set to 48 MHz, with a prescaler of 24'000 |
| 116 | + // we'll get ticks that are 0.5 ms long. This means that we can write the |
| 117 | + // delay value multipled by two to the auto-reload register (ARR). |
| 118 | + // |
| 119 | + // Note that we cannot simply use a prescaler value where the tick corresponds |
| 120 | + // to 1 ms, because then a clock of 100 MHz would correspond to a prescaler |
| 121 | + // value of 100'000, which doesn't fit in the 16-bit PSC register. |
| 122 | + // |
| 123 | + // Unfortunately this means that only one half of the full 32-bit range |
| 124 | + // can be used, but 24 days should be plenty of usable delay time. |
| 125 | + let psc = u16(self.clocks.pclk1().0 / 1000 / 2) |
| 126 | + .expect("Prescaler does not fit in u16"); |
| 127 | + |
| 128 | + // Since PSC = 0.5 ms, double the value for the ARR |
| 129 | + let arr = ms << 1; |
| 130 | + |
| 131 | + $waitfn(&mut self.tim, psc, arr); |
| 132 | + } |
| 133 | + } |
| 134 | + |
| 135 | + impl DelayMs<u16> for $struct { |
| 136 | + /// Sleep for up to (2^16)-1 milliseconds (~65 seconds). |
| 137 | + fn delay_ms(&mut self, ms: u16) { |
| 138 | + // See DelayMs<u32> for explanations. Since the value range is only 16 bit, |
| 139 | + // we don't need an assert here. |
| 140 | + let psc = u16(self.clocks.pclk1().0 / 1000 / 2) |
| 141 | + .expect("Prescaler does not fit in u16"); |
| 142 | + let arr = u32(ms) << 1; |
| 143 | + $waitfn(&mut self.tim, psc, arr); |
| 144 | + } |
| 145 | + } |
| 146 | + )+ |
| 147 | + } |
| 148 | +} |
| 149 | + |
| 150 | +#[cfg(any( |
| 151 | + feature = "stm32f401", |
| 152 | + feature = "stm32f405", |
| 153 | + feature = "stm32f407", |
| 154 | + feature = "stm32f410", |
| 155 | + feature = "stm32f411", |
| 156 | + feature = "stm32f412", |
| 157 | + feature = "stm32f413", |
| 158 | + feature = "stm32f415", |
| 159 | + feature = "stm32f417", |
| 160 | + feature = "stm32f423", |
| 161 | + feature = "stm32f427", |
| 162 | + feature = "stm32f429", |
| 163 | + feature = "stm32f437", |
| 164 | + feature = "stm32f439", |
| 165 | + feature = "stm32f446", |
| 166 | + feature = "stm32f469", |
| 167 | + feature = "stm32f479" |
| 168 | +))] |
| 169 | +hal! { |
| 170 | + TIM5: (Tim5Delay, wait_tim5, 3, apb1enr, apb1rstr, pclk1, ppre1), |
| 171 | +} |
| 172 | + |
| 173 | +#[cfg(any( |
| 174 | + feature = "stm32f401", |
| 175 | + feature = "stm32f405", |
| 176 | + feature = "stm32f407", |
| 177 | + feature = "stm32f411", |
| 178 | + feature = "stm32f412", |
| 179 | + feature = "stm32f413", |
| 180 | + feature = "stm32f415", |
| 181 | + feature = "stm32f417", |
| 182 | + feature = "stm32f423", |
| 183 | + feature = "stm32f427", |
| 184 | + feature = "stm32f429", |
| 185 | + feature = "stm32f437", |
| 186 | + feature = "stm32f439", |
| 187 | + feature = "stm32f446", |
| 188 | + feature = "stm32f469", |
| 189 | + feature = "stm32f479" |
| 190 | +))] |
| 191 | +hal! { |
| 192 | + TIM2: (Tim2Delay, wait_tim2, 0, apb1enr, apb1rstr, pclk1, ppre1), |
| 193 | +} |
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